LPC2141 PHILIPS [NXP Semiconductors], LPC2141 Datasheet
LPC2141
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LPC2141 Summary of contents
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... USB 2.0 Full-speed compliant device controller with endpoint RAM. In addition, the LPC2146/48 provides on-chip RAM accessible to USB by DMA. One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 s per channel. Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). ...
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... LPC2142FBD64 LPC2144FBD64 LPC2146FBD64 LPC2148FBD64 3.1 Ordering options Table 2: Type number LPC2141FBD64 32 kB LPC2142FBD64 64 kB LPC2144FBD64 128 kB LPC2146FBD64 256 kB LPC2148FBD64 512 kB [1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage. ...
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... AHB BRIDGE (Advanced High-performance Bus) INTERNAL FLASH CONTROLLER 32 kB/64 kB/128 kB/ AHB TO VPB 256 kB/512 kB BRIDGE FLASH VPB (VLSI peripheral bus) (2) PWM0 Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers XTAL2 XTAL1 RST PLL0 SYSTEM system FUNCTIONS clock PLL1 VECTORED USB INTERRUPT clock ...
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... P1.18/TRACEPKT2 8 P0.25/AD0 P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 2. LPC2141 pinning 9397 750 14985 Preliminary data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2141 Rev. 01 — 3 October 2005 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/EINT2 44 P1.21/PIPESTAT0 43 ...
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... P1.17/TRACEPKT1 12 P0.28/AD0.1/CAP0.2/MAT0 P0.29/AD0.2/CAP0.3/MAT0.3 P0.30/AD0.3/EINT3/CAP0.0 15 P1.16/TRACEPKT0 16 Fig 3. LPC2142 pinning 9397 750 14985 Preliminary data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2142 Rev. 01 — 3 October 2005 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/EINT2 44 P1.21/PIPESTAT0 ...
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... P1.17/TRACEPKT1 12 13 P0.28/AD0.1/CAP0.2/MAT0.2 P0.29/AD0.2/CAP0.3/MAT0.3 14 P0.30/AD0.3/EINT3/CAP0 P1.16/TRACEPKT0 Fig 4. LPC2144/2146/2148 pinning 9397 750 14985 Preliminary data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers LPC2144/2146/2148 Rev. 01 — 3 October 2005 48 P1.20/TRACESYNC 47 P0.17/CAP1.2/SCK1/MAT1.2 46 P0.16/EINT0/MAT0.2/CAP0.2 45 P0.15/RI1/EINT2/AD1.5 44 P1.21/PIPESTAT0 ...
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... TXD1 — Transmitter output for UART1. O PWM4 — Pulse Width Modulator output 4. I AD1.1 — ADC 1, input 1. Available in LPC2144/46/48 only. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 2 C-bus compliance). 2 C-bus compliance). © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... CAP1.2 — Capture input for Timer 1, channel 2. I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave. O MAT1.2 — Match output for Timer 1, channel 2. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 2 C-bus compliance) 2 C-bus compliance) © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... P0.30 — General purpose input/output digital pin (GPIO). I AD0.3 — ADC 0, input 3. I EINT3 — External interrupt 3 input. I CAP0.0 — Capture input for Timer 0, channel 0. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Note: LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate as Debug port after reset. I/O P1.27 — General purpose input/output digital pin (GPIO). O TDO — Test Data out for JTAG interface. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... RTC power supply voltage: 3 this pin supplies the power to the RTC. 2 C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... The impact on the overall code size will be minimal but the speed can be increased over Thumb mode. 6.2 On-chip flash program memory The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the fl ...
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... On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB and static RAM respectively. In case of LPC2146/48 only SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution ...
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... Trace pins will assume their trace functionality. The pins associated with the I 9397 750 14985 Preliminary data sheet and I C1 interface are open drain. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/ and for LPC2144/46/48 is 14. 6.8.1 Features • ...
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... LPC2146/48). • Double buffer implementation for bulk and isochronous endpoints. 6.11 UARTs The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS fl ...
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... The I 6.13 SPI serial I/O controller The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer ...
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... Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts ...
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... Dedicated power supply pin can be connected to a battery or the main 3.3 V. 9397 750 14985 Preliminary data sheet 256 PCLK 4. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers multiples of PCLK © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Pulse width modulator The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. ...
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... The PLL settling time is 100 s. 6.19.3 Reset and wake-up timer Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fi ...
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... V detection to reliably interrupt regularly-executed event loop to sense the condition. 6.19.5 Code security This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in fl ...
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... Idle mode. 6.20 Emulation and debugging The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself ...
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... The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. 6.20.2 Embedded trace Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores ...
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... Per ground pin. [11] Dependent on package type. 9397 750 14985 Preliminary data sheet Conditions [3] for the RTC [ tolerant I/O pins other I/O pins [10] [11] based on package heat transfer, not device power consumption Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] Min Max 0.5 +3.6 0.5 4.6 0.5 4.6 0.5 4.6 0.5 5.1 [5] [6] 0.5 6.0 [5] 0 ...
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... 3 code DD a while(1){} executed from flash, no active peripherals CCLK = 10 MHz CCLK = 60 MHz (other parameters as above Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 [3] 2.0 3.3 3.6 2.5 3.3 V DDA - - 3 - ...
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... CCLK = 60 MHz OLS [13 < V < 3 includes V range DI Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ Max <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> <tbd> ...
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... See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 6. Figure Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] Min Typ - - 2 ...
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... LSB (ideal (LSB ) ia ideal ). D ). Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers (1) 1018 1019 1020 1021 1022 1023 V V DDA SSA 1 LSB = 1024 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. offset gain error error ...
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... Philips Semiconductors ADx.y Fig 7. Suggested ADC interface - LPC2141/42/44/46/48 ADx.y pin 9397 750 14985 Preliminary data sheet LPC2141/42/44/46/ SAMPLE Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers R vsi ADx.y V EXT 002aab834 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... Figure 9 see Figure [1] must reject as EOP; see Figure 9 [1] must accept as EOP; see Figure 9 over specified ranges DD Conditions Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers Min Typ Max 110 1.3 - 2.0 160 - 175 2 ...
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... Fig 8. External clock timing t PERIOD differential data lines Fig 9. Differential data-to-EOP transition skew and EOP width 10. Application information 10.1 Suggested USB interface solutions LPC2142/2148 Fig 10. LPC2141/42/44/46/48 USB interface using the CONNECT function on pin 17 9397 750 14985 Preliminary data sheet 0 0 ...
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... Philips Semiconductors LPC2141/42/ 44/46/48 Fig 11. LPC2141/42/44/46/48 USB interface using the UP_LED function on pin 17 9397 750 14985 Preliminary data sheet LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 1.5 k UP_LED VBUS Rev. 01 — 3 October 2005 USB-B connector 002aab562 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... 0.27 0.18 10.1 10.1 12.15 12.15 0.5 0.17 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers detail 0.75 1.45 1 0.2 0.12 0.1 0.45 1.05 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. SOT314-2 ...
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... Pulse Width Modulator Random Access Memory Serial Peripheral Interface Static Random Access Memory Synchronous Serial Port Universal Asynchronous Receiver/Transmitter Universal Serial Bus VLSI Peripheral Bus Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... LPC2141_42_44_46_48_1 9397 750 14985 Preliminary data sheet Release Data sheet status date 20051003 Preliminary data sheet Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers Change Doc. number Supersedes notice - 9397 750 14985 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... I C-bus — wordmark and logo are trademarks of Koninklijke Philips Electronics N.V. SoftConnect — trademark of Koninklijke Philips Electronics N.V. Rev. 01 — 3 October 2005 LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 19 6.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.18 Pulse width modulator . . . . . . . . . . . . . . . . . . 20 6.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.19 System control . . . . . . . . . . . . . . . . . . . . . . . . 21 6.19.1 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 21 6.19.2 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.19.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 21 6.19.4 Brownout detector LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.19.5 Code security . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.19.6 External interrupt inputs . . . . . . . . . . . . . . . . . 22 6.19.7 Memory mapping control . . . . . . . . . . . . . . . . 22 6.19.8 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19.9 VPB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.20 Emulation and debugging 6.20.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 23 6.20.2 Embedded trace ...