LPC2364_10 NXP [NXP Semiconductors], LPC2364_10 Datasheet
LPC2364_10
Related parts for LPC2364_10
LPC2364_10 Summary of contents
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LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 06 — 1 February 2010 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation ...
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NXP Semiconductors Serial interfaces: Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed device with on-chip PHY and associated DMA controller (LPC2364/66/68 only). Four UARTs with fractional baud rate generation, one with modem ...
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NXP Semiconductors On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. Boundary scan for simplified ...
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Ordering options Table 2. Ordering options Type number Flash SRAM (kB) (kB) Local Ethernet GP/USB RTC bus buffers LPC2364FBD100 128 LPC2364HBD100 128 LPC2364FET100 128 LPC2365FBD100 256 LPC2366FBD100 ...
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NXP Semiconductors 5. Block diagram LPC2364/65/66/67/68 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 70 PINS TOTAL ETHERNET RMII(8) MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2, TIMER2/TIMER3 2 × ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 TDO 2 5 P1[10]/ENET_RXD1 6 9 P0[7]/I2STX_CLK/ 10 SCK1/MAT2[1] Row B 1 TMS 2 LPC2364_65_66_67_68_6 Product data ...
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NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 9 P2[0]/PWM1[1]/ 10 TXD1/TRACECLK Row C 1 TCK 2 5 P1[8]/ENET_CRS Row D 1 P0[24]/AD0[1]/ 2 I2SRX_WS/CAP3[1] 5 P1[0]/ENET_TXD0 6 9 ...
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NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0 2 5 P1[22]/MAT1[ P2[13]/EINT3/ 10 MCIDAT3/I2STX_SDA Row K 1 P3[26]/MAT0[1]/ 2 PWM1[3] 5 P1[23]/PWM1[4]/ 6 MISO0 9 P0[11]/RXD2/ 10 SCL2/MAT3[1] 6.2 Pin description ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[6 I2SRX_SDA/ SSEL1/MAT2[0] [1] [1] P0[7 I2STX_CLK/ SCK1/MAT2[1] [1] P0[8 I2STX_WS/ MISO1/MAT2[2] [1] P0[9]/ 76 A10 I2STX_SDA/ MOSI1/MAT2[3] [1] P0[10]/TXD2 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P0[18]/DCD1 MOSI0/MOSI [1] P0[19]/DSR1/ 59 G10 MCICLK/SDA1 [1] P0[20]/DTR1 MCICMD/SCL1 [1] P0[21]/RI1 MCIPWR/RD1 [1] P0[22]/RTS1/ 56 H10 MCIDAT0/TD1 [2] [2] P0[23]/AD0[0]/ 9 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [4] [4] P0[27]/SDA0 25 J2 [4] [4] P0[28]/SCL0 24 J1 [5] [5] P0[29]/USB_D [5] P0[30]/USB_D− P1[0] to P1[31] [1] P1[0 ENET_TXD0 [1] [1] P1[1]/ ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] [1] P1[20]/PWM1[2 SCK0 [1] [1] P1[21]/PWM1[3 SSEL0 [1] [1] P1[22]/MAT1[ [1] [1] P1[23]/PWM1[4 MISO0 [1] P1[24]/PWM1[5 MOSI0 [1] P1[25]/MAT1[1] ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[1]/PWM1[2]/ 74 B10 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3 CTS1/ PIPESTAT1 [1] [1] P2[3]/PWM1[4 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5 DSR1/ TRACESYNC [1] P2[5]/PWM1[6]/ 68 D10 DTR1/ ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] P2[11]/EINT1 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 51 K10 MCIDAT2/ I2STX_WS [6] [6] P2[13]/EINT3 MCIDAT3/ I2STX_SDA P3[0] to P3[31] [1] P3[25]/MAT0[0 PWM1[2] [1] [1] P3[26]/MAT0[1]/ ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] TCK 5 C1 [1] [1] RTCK 100 B2 RSTOUT 14 - [7] [7] RESET 17 F3 [8][9] XTAL1 22 H2 [8][9] XTAL2 23 G3 [8] [8] RTCX1 16 F2 ...
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NXP Semiconductors [8] Pad provides special analog functionality. [9] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 ...
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NXP Semiconductors The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that ...
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NXP Semiconductors 3.75 GB Fig 4. 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or ...
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NXP Semiconductors FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one ...
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NXP Semiconductors • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, ...
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NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, ...
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NXP Semiconductors – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame ...
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NXP Semiconductors • Double buffer implementation for Bulk and Isochronous endpoints. 7.11 CAN controller and acceptance filters (LPC2364/66/68 only) The Controller Area Network (CAN serial communications protocol which efficiently supports distributed real-time control with a very high level ...
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NXP Semiconductors 7.13 10-bit DAC The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The maximum output value of the DAC is V 7.13.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode ...
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NXP Semiconductors 7.16 SSP serial I/O controller The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. ...
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NXP Semiconductors 7.18.1 Features • standard I • and I devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate ...
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NXP Semiconductors 7.20 General purpose 32-bit timers/external event counters The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions ...
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NXP Semiconductors Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge ...
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NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be ...
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NXP Semiconductors 7.24.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is ...
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NXP Semiconductors When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses clock source and starts to execute instructions. This is important ...
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NXP Semiconductors On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will ...
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NXP Semiconductors The first option assumes that power consumption is not a concern and the design ties the V DD(3V3) supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the ...
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NXP Semiconductors 7.25.3 Code security (Code Read Protection - CRP) This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP ...
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NXP Semiconductors 7.25.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. ...
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NXP Semiconductors Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.26.3 RealMonitor RealMonitor is a configurable software module, developed by ARM ...
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NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad ...
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NXP Semiconductors 9. Static characteristics Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 ...
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NXP Semiconductors Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter I I/O latch-up current latch V input voltage I V output voltage O V HIGH-level input IH voltage ...
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NXP Semiconductors Table 6. Static characteristics − ° ° +85 C for standard devices, amb Symbol Parameter USB pins (LPC2364/66/68 only) I OFF-state output OZ current V bus supply voltage BUS V differential input DI ...
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NXP Semiconductors 9.1 Power-down mode I DD(IO) (μA) Fig 5. I (μA) Fig 6. LPC2364_65_66_67_68_6 Product data sheet −2 −4 −40 − 3 i(VBAT) DD(DCDC)(3V3) amb I/O maximum supply current I ...
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NXP Semiconductors I DD(DCDC)pd(3v3) Fig 7. 9.2 Deep power-down mode I DD(IO) (μA) Fig 8. LPC2364_65_66_67_68_6 Product data sheet 800 (μA) 600 400 V = 3.3 V DD(DCDC)(3V3) 200 V = 3.0 V DD(DCDC)(3V3) 0 −40 − ...
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NXP Semiconductors I (μA) Fig 9. I DD(DCDC)dpd(3v3) Fig 10. Total DC-to-DC converter maximum supply current I LPC2364_65_66_67_68_6 Product data sheet 40 BAT 3.3 V i(VBAT 3.0 V i(VBAT −40 −15 V ...
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NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics − ° ° +85 C for standard devices, amb [1] over specified ranges. Symbol Parameter ARM processor clock frequency f operating frequency oper External clock f ...
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NXP Semiconductors Table 8. Dynamic characteristics of USB pins (full-speed) Ω pF 1 Symbol Parameter t receiver jitter for paired transitions JR2 t EOP width at receiver EOPR1 ...
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NXP Semiconductors 10.1 Timing Fig 11. External clock timing (with an amplitude of at least V T PERIOD differential data lines Fig 12. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 13. MISO line set-up ...
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NXP Semiconductors 11. ADC electrical characteristics Table 10. ADC characteristics − 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D ...
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NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity ...
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NXP Semiconductors AD0[y] Fig 15. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin LPC2364_65_66_67_68_6 Product data sheet LPC23XX 20 kΩ SAMPLE Rev. 06 — 1 February 2010 LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers R vsi AD0[y] V ...
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NXP Semiconductors 12. DAC electrical characteristics Table 11. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E ...
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NXP Semiconductors LPC23XX Fig 17. LPC2364/66/68 USB interface on a bus-powered device 13.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode ...
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NXP Semiconductors 14. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original ...
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NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index ...
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NXP Semiconductors 15. Abbreviations Table 12. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII MIIM PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB LPC2364_65_66_67_68_6 Product data sheet Abbreviations ...
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NXP Semiconductors 16. Revision history Table 13. Revision history Document ID LPC2364_65_66_67_68_6 Modifications: LPC2364_65_66_67_68_5 Modifications: LPC2364_65_66_67_68_4 LPC2364_66_68_3 LPC2364_66_68_2 LPC2364_66_68_1 LPC2364_65_66_67_68_6 Product data sheet Release date Data sheet status 20100201 Product data sheet • Table 5 “Limiting values”: Changed V • ...
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NXP Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors ...
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NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 13.3 XTAL and RTC Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 51 14 Package outline . . . . . . . . ...