LPC2420FBD208 NXP [NXP Semiconductors], LPC2420FBD208 Datasheet - Page 43

• Manufacturer Part Number: LPC2420FBD208
• Description: Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2420_60_3
Preliminary data sheet
7.25.3 Brownout detection
7.25.4 AHB
7.25.5 External interrupt inputs
7.25.6 Memory mapping control
Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped.
The user code residing in the external boot memory must be linked to execute from
address location 0x8000 0000.
When booting from external memory, the interrupt vectors are mapped to the bottom of
the external memory. Once booting is over, the application must map interrupt vectors to
the proper domain.
The LPC2420/2460 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
The second stage of low-voltage detection asserts a BOD Reset and generates a Reset
(if this reset source is enabled in software) to inactivate the LPC2420/2460 when the
voltage on the V
below 1 V, at which point the power-on reset circuitry maintains the overall Reset.
Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
The LPC2460 implements two AHB in order to allow the Ethernet block to operate without
interference caused by other system activity. The primary AHB, referred to as AHB1, is
implemented on LPC2420 as well and includes the Vectored Interrupt Controller, GPDMA
controller, USB interface, and 16 kB SRAM.
The second AHB, referred to as AHB2, is implemented on LPC2460 only and includes
only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is
provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion
of Ethernet buffer space into off-chip memory or unused space in memory residing on
AHB1.
In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the
GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters
with access to AHB2 are the ARM7 and the Ethernet block.
The LPC2420/2460 includes up to 68 edge sensitive interrupt inputs combined with up to
four level sensitive external interrupt inputs as selectable pin functions. The external
interrupt inputs can optionally be used to wake up the processor from Power-down mode.
The memory mapping control alters the mapping of the interrupt vectors that appear at the
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot
ROM, the SRAM, or external memory. This allows code running in different memory
spaces to have control of the interrupts.
DD(3V3)
Rev. 03 — 20 November 2008
pins falls below 2.65 V. The BOD circuit maintains this reset down
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2008. All rights reserved.
DD(3V3)
pins. If this
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