LPC1767 NXP [NXP Semiconductors], LPC1767 Datasheet
LPC1767
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LPC1767 Summary of contents
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LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 04 — 1 February 2010 1. General description The LPC1769/68/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring ...
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NXP Semiconductors Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General ...
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NXP Semiconductors Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. ...
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... Ordering options Type number Flash SRAM in kB CPU AHB LPC1769FBD100 512 kB 32 LPC1768FBD100 512 kB 32 LPC1767FBD100 512 kB 32 LPC1766FBD100 256 kB 32 LPC1765FBD100 256 kB 32 LPC1764FBD100 128 kB 16 LPC1769_68_67_66_65_64_4 Product data sheet Description plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm plastic low profile quad flat package ...
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NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE ARM CORTEX-M3 I-code D-code bus bus P0 to HIGH-SPEED P4 GPIO APB slave group 0 SCK1 SSEL1 SSP1 MISO1 MOSI1 RXD0/TXD0 UART0/1 8 × UART1 RD1/2 CAN1/2 TD1/2 SCL0/1 ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Pin description Symbol Pin Type P0[0] to P0[31] I/O [1] P0[0]/RD1/TXD3/ 46 I/O SDA1 I O I/O [1] P0[1]/TD1/RXD3/ 47 I/O SCL1 O I I/O [2] ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[5]/ 80 I/O I2SRX_WS/ I/O TD2/CAP2[ [1] P0[6]/ 79 I/O I2SRX_SDA/ I/O SSEL1/MAT2[0] I/O O [1] P0[7]/ 78 I/O I2STX_CLK/ I/O SCK1/MAT2[1] I/O O [1] P0[8]/ 77 ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P0[16]/RXD1/ 63 I/O SSEL0/SSEL I I/O I/O [1] P0[17]/CTS1/ 61 I/O MISO0/MISO I I/O I/O [1] P0[18]/DCD1/ 60 I/O MOSI0/MOSI I I/O I/O [1] P0[19]/DSR1/ 59 I/O SDA1 I ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [2] P0[25]/AD0[2]/ 7 I/O I2SRX_SDA/ I TXD3 I/O O [3] P0[26]/AD0[3]/ 6 I/O AOUT/RXD3 [4] P0[27]/SDA0/ 25 I/O USB_SDA I/O I/O [4] P0[28]/SCL0/ 24 I/O USB_SCL I/O ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[16]/ 87 I/O ENET_MDC O [1] P1[17]/ 86 I/O ENET_MDIO I/O [1] P1[18]/ 32 I/O USB_UP_LED/ O PWM1[1]/ CAP1[ [1] P1[19]/MCOA0/ 33 I/O USB_PPWR O CAP1[1] O ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P1[26]/MCOB1/ 40 I/O PWM1[6]/CAP0[ [1] P1[27]/CLKOUT 43 I/O /USB_OVRCR/ O CAP0[ [1] P1[28]/MCOA2/ 44 I/O PCAP1[0]/ O MAT0[ [1] P1[29]/MCOB2/ 45 I/O ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [1] P2[4]/PWM1[5]/ 69 I/O DSR1/ O TRACEDATA[ [1] P2[5]/PWM1[6]/ 68 I/O DTR1/ O TRACEDATA[ [1] P2[6]/PCAP1[0]/ 67 I/O RI1/TRACECLK [1] P2[7]/RD2/ 66 I/O ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [6] P2[13]/EINT3/ 50 I/O I2STX_SDA I I/O P3[0] to P3[31] I/O [1] P3[25]/MAT0[0]/ 27 I/O PWM1[ [1] P3[26]/STCLK/ 26 I/O MAT0[1]/PWM1[ P4[0] to P4[31] I/O ...
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NXP Semiconductors Table 3. Pin description …continued Symbol Pin Type [8] RTCX2 31, 41 55, 72, [8] 97 SSA V 28, 54, I DD(3V3) [8] 71, 96 [8] V 42, ...
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NXP Semiconductors 7. Functional description 7.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see system bus ...
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NXP Semiconductors The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The ...
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APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved 0x400C 0000 QEI 15 0x400B C000 14 motor control PWM 0x400B 8000 reserved 13 0x400B 4000 repetitive interrupt timer 12 0x400B 0000 reserved 11 0x400A C000 (1) ...
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NXP Semiconductors 7.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.7.1 Features • Controls system ...
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NXP Semiconductors 7.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst ...
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NXP Semiconductors Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, ...
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NXP Semiconductors – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check ...
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NXP Semiconductors • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, ...
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NXP Semiconductors 7.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) ...
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NXP Semiconductors 7.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic ...
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NXP Semiconductors data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of ...
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NXP Semiconductors 2 7.20 I S-bus serial I/O controllers Remark: The I 2 The I S-bus provides a standard communication interface for digital audio applications. 2 The I S-bus specification defines a 3-wire serial bus using one data line, one ...
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NXP Semiconductors • four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • two match ...
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NXP Semiconductors • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can ...
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NXP Semiconductors • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 7.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which ...
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NXP Semiconductors conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 7.28 RTC ...
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NXP Semiconductors See Figure 4 LPC17xx MAIN OSCILLATOR INTERNAL RC OSCILLATOR 32 kHz RTC OSCILLATOR Fig 4. LPC17xx clocking generation block diagram 7.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as ...
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NXP Semiconductors 7.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock ...
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NXP Semiconductors whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. ...
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NXP Semiconductors The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip ...
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NXP Semiconductors 7.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered ...
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NXP Semiconductors Fig 5. 7.30 System control 7.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. ...
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NXP Semiconductors 7.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the V voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in ...
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NXP Semiconductors 7.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the ...
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NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V regulator supply voltage (3.3 V) DD(REG)(3V3) V analog 3.3 V pad supply ...
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NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often ...
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NXP Semiconductors 10. Static characteristics Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3.3 V) ...
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NXP Semiconductors Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Standard port pins, RESET, RTCK I LOW-level input current HIGH-level input IH current I OFF-state ...
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NXP Semiconductors Table 6. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 V input ...
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NXP Semiconductors [15] Accounts for 100 mV voltage drop in all supply lines. [16] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [17 [18] Includes external resistors ...
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NXP Semiconductors (μA) Fig 8. (μA) Fig 9. LPC1769_68_67_66_65_64_4 Product data sheet −10 − °C 25 °C −40 °C −50 − Conditions DD(REG)(3V3) DD(3V3) Typical pull-up current I versus ...
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NXP Semiconductors 11. Dynamic characteristics 11.1 Flash memory Table 7. Flash characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter N endurance endu t retention time ret [1] Number of program/erase cycles. ...
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NXP Semiconductors 11.3 Internal oscillators Table 9. Dynamic characteristic: internal oscillators − ° ° ≤ +85 C; 2.7 V amb Symbol Parameter f internal RC oscillator frequency osc(RC) f RTC input frequency i(RTC) [1] Parameters ...
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NXP Semiconductors 2 11.5 I C-bus Table 11. Dynamic characteristic: I − ° ° + amb DD(3V3) Symbol Parameter f SCL clock frequency SCL t fall time f t data set-up time SU;DAT ...
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NXP Semiconductors I2STX_CLK I2STX_SDA I2STX_WS Fig 13. I I2SRX_CLK I2SRX_SDA I2SRX_WS Fig 14. I LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 T cy(clk v(Q) t v(Q) 2 S-bus timing (output) T cy(clk S-bus timing (input) Rev. ...
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NXP Semiconductors 11.7 SSP interface Table 13. Dynamic characteristic: SSP interface ° over specified ranges. amb DD(3V3) Symbol Parameter SSP interface t SPI_MISO set-up time su(SPI_MISO) [1] The peripheral clock for SSP is PCLK = ...
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NXP Semiconductors 11.8 USB interface (LPC1769/68/66/65/64 only) Table 14. Dynamic characteristics: USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t ...
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NXP Semiconductors 11.9 SPI Table 15. − amb Symbol T cy(PCLK) T SPICYC t SPICLKH t SPICLKL SPI master t SPIDSU t SPIDH t SPIQV t SPIOH SPI slave t SPIDSU t SPIDH t SPIQV t SPIOH [1] ...
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NXP Semiconductors Fig 18. Fig 19. LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI DATA VALID MISO SPI master timing (CPHA = 0) T SPICYC SCK (CPOL = 0) SCK ...
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NXP Semiconductors Fig 20. 12. ADC electrical characteristics Table 16. ADC characteristics − 2 3 DDA amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity ...
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NXP Semiconductors 4095 4094 4093 4092 4091 4090 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity ...
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NXP Semiconductors Fig 22. ADC interface to pins AD0[n] 13. DAC electrical characteristics (LPC1769/68/67/66/65 only) Table 17. DAC electrical characteristics − 2 3 DDA amb Symbol Parameter E differential linearity error D ...
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NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions LPC17xx Fig 23. LPC1769/68/66/65/64 USB interface on a self-powered device LPC17xx Fig 24. LPC1769/68/66/65/64 USB interface on a bus-powered device LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/64 32-bit ARM Cortex-M3 microcontroller V ...
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NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 25. LPC1769/68/66/65 USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 26. LPC1769/68/66/65 USB host port configuration LPC1769_68_67_66_65_64_4 Product data sheet LPC1769/68/67/66/65/ RESET_N ADR/PSW ...
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NXP Semiconductors USB_UP_LED USB_CONNECT LPC17xx USB_D+ USB_D− V BUS Fig 27. LPC1769/68/66/65/64 USB device port configuration 14.2 XTAL1 input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in ...
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NXP Semiconductors 15. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original ...
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NXP Semiconductors 16. Abbreviations Table 18. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB ...
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... V. 20091119 Product data sheet • Changed data sheet status to Product data sheet. • Added part LPC1767. • Maximum data bit rate for SPI, SSP, UART added. • RTC backup RAM size updated (20 bytes). • WDT clock source added: RTC oscillator. ...
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NXP Semiconductors 18. Legal information 19. Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use ...
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NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 7.30.7 Memory mapping control . . . . . . . . . . . . . . . . 38 7.31 Emulation and debugging . . . . . . . . . . . . . ...