R5F21133DFP RENESAS [Renesas Technology Corp], R5F21133DFP Datasheet
R5F21133DFP
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R5F21133DFP Summary of contents
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REJ09B0111-0120 16 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published ...
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Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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How to Use This Manual 1. Introduction This hardware manual provides detailed information on the R8C/13 Group of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, ...
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M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE NOTES: 1. Before using this material, please visit the our website to verify ...
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Table of Contents SFR Page Reference Chapter 1. Overview .............................................................. 1 1.1 Applications .................................................................................................................... 1 1.2 Performance Overview ................................................................................................... 2 1.3 Block Diagram ................................................................................................................ 3 1.4 Product Information ....................................................................................................... 4 1.5 Pin Assignments............................................................................................................. 5 1.6 Pin Description ............................................................................................................... 6 Chapter ...
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Voltage Detection Circuit ............................................................................................. 21 5.4.1 Voltage Detection Interrupt .................................................................................................................. 26 5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt ......................................................................... 28 Chapter 6. Clock Generating Circuit.................................. 29 6.1 Main Clock ..................................................................................................................... 34 6.2 On-Chip Oscillator Clock ............................................................................................. 35 ...
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Timer Mode .......................................................................................................................................... 73 12.1.2 Pulse Output Mode ............................................................................................................................. 74 12.1.3 Event Counter Mode ........................................................................................................................... 75 12.1.4 Pulse Width Measurement Mode ....................................................................................................... 76 12.1.5 Pulse Period Measurement Mode ..................................................................................................... 78 12.2 Timer Y......................................................................................................................... 80 12.2.1 Timer Mode .......................................................................................................................................... 83 ...
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Chapter 16. Electrical Characteristics ............................. 152 Chapter 17. Flash Memory Version ................................. 165 17.1 Overview .................................................................................................................... 165 17.2 Memory Map .............................................................................................................. 166 17.3 Functions To Prevent Flash Memory from Rewriting............................................ 167 17.3.1 ID Code Check Function .................................................................................................................. 167 17.4 CPU ...
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Noise .......................................................................................................................... 198 Chapter 20. Usage Notes for On-chip Debugger ............ 199 Appendix 1 Package Dimensions .................................... 200 Appendix 2 Connecting Examples for Serial Writer and On-chip Debugging Emulator .......................................... 201 Appendix 3 Example of Oscillation Evaluation Circuit .. ...
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SFR Page Reference ...
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SFR Page Reference ...
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R8C/13 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview This MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions ...
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R8C/13 Group 1.2 Performance Overview Table 1.1. lists the performance outline of this MCU. Table 1.1 Performance outline Item CPU Number of basic instructions 89 instructions Minimum instruction execution time Operating mode Address space Memory capacity Peripheral Port function LED ...
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R8C/13 Group 1.3 Block Diagram Figure 1.1 shows this MCU block diagram ...
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... Table 1.2 Product Information Type No. Program ROM 8K bytes R5F21132FP 12K bytes R5F21133FP R5F21134FP 16K bytes R5F21132DFP 8K bytes R5F21133DFP 12K bytes R5F21134DFP 16K bytes Type No Figure 1.2 Type No., Memory Size, and Package Rev.1.20 Jan 27, 2006 page 4 of 205 REJ09B0111-0120 ROM capacity ...
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R8C/13 Group 1.5 Pin Assignments Figure 1.3 shows the pin configuration (top view). PIN Assignments (top view /AN /TxD 0 ...
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R8C/13 Group 1.6 Pin Description Table 1.3 shows the pin description Table 1.3 Pin description Signal name Pin name Power supply Vcc, input Vss IVcc IVcc Analog power AVcc, AVss supply input ___________ Reset input RESET CNVss CNVss MODE MODE ...
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R8C/13 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided. b ...
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R8C/13 Group 2.2 Address Registers (A0 and A1 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies A0. ...
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... Expansion area FFFFF 16 NOTES: 1. The data flash block A (2K bytes) and block B (2K bytes) are shown. 2. Blank spaces are reserved. No access is allowed. Type name R5F21134FP, R5F21134DFP R5F21133FP, R5F21133DFP R5F21132FP, R5F21132DFP Figure 3.1 Memory Map Rev.1.20 Jan 27, 2006 page 9 of 205 REJ09B0111-0120 to 007FF ...
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R8C/13 Group 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information Table 4.1 SFR Information( ...
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R8C/13 Group Table 4.2 SFR Information( ...
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R8C/13 Group Table 4.3 SFR Information( ...
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R8C/13 Group Table 4.4 SFR Information( ...
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R8C/13 Group 5. Reset There are three types of resets: a hardware reset, a software reset, and an watchdog timer reset. 5.1 Hardware Reset There are three kinds of hardware reset: hardware reset 1, hardware reset 2, and power-on reset. ...
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R8C/13 Group b15 b19 Content of addresses 0FFFE b15 b15 b15 IPL Figure 5.1 CPU Register Status After Reset ...
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R8C/13 Group V RESET CC Figure 5.3 Example Reset Circuit Using The Hardware Reset 1 RESET V CC Figure 5.4 Example Reset Circuit Using The Hardware Reset 1 (Voltage Check Circuit) Rev.1.20 Jan 27, 2006 page 16 of 205 REJ09B0111-0120 ...
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R8C/13 Group 5.1.2 Hardware Reset 2 This is the reset generated by the voltage detection circuit which is built-in to the microcomputer. The voltage detection circuit monitors the input voltage at Vcc input pin. The microcomputer is reset when the ...
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R8C/13 Group 5.1.3 Power-on Reset Function The power-on reset is the function which can reset the microcomputer without the external reset ____________ circuit. The RESET pin should be connected to the V the power-on reset function, the function turns to ...
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R8C/13 Group RESET Vcc about 5 k det por1 t w(por1) Internal reset signal (“L” effective) NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time sampling clock ...
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R8C/13 Group 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized. Then the program is executed starting from the address indicated by the ...
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R8C/13 Group 5.4 Voltage Detection Circuit The voltage detection circuit monitors the input voltage at the V program can check for voltage detection using the VC13 bit or set up the voltage detection interrupt register to generate a hardware reset ...
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R8C/13 Group 5 det V CC Internal reset signal (D46 bit=1) VC13 bit VC27 bit Voltage detection interrupt request (D46 bit=0) The above applies to the following conditions. • D4INT register D40 bit = 1 (voltage detection interrupt ...
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R8C/13 Group 5.0V V det V CC Internal reset signal(D46 bit = 1) VC13 bit VC27 bit CM 10 bit Voltage detection interrupt request (D46 bit = 0) The above applies to the following conditions. D4INT register D40 = 1 ...
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R8C/13 Group 5.4.1 Voltage Detection Interrupt Figure 5.13 shows the block diagram of voltage detection interrupt generation circuit. Refer to 5.4.2, "Exiting Stop Mode on a Voltage Detection Circuit" for Getting out of stop mode due to the voltage detection ...
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R8C/13 Group Voltage detection circuit VC27 f RING-S VC13 V + CC1 Noise canceller Voltage - detection Internal (Canceller width: 200 ns) reference signal voltage Voltage detection signal is “H” when VC27 bit= 0 (disabled) CM10 Watchdog timer block Watchdog ...
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R8C/13 Group 5.4.2 Exiting Stop Mode on a Voltage Detection Interrupt A voltage detection interrupt is generated when the input voltage at the V or drops below Vdet if all of the following conditions hold true in stop mode. • ...
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R8C/13 Group 6. Clock Generation Circuit The clock generation circuit contains two oscillator circuits as follows: • Main clock oscillation circuit • On-chip oscillator (with oscillation stop detection function) Table 6.1 lists the clock generation circuit specifications. Figure 6.1 shows ...
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R8C/13 Group The following describes the clocks generated by the clock generation circuit. 6.1 Main Clock This clock is supplied by a main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function ...
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R8C/13 Group 6.2 On-Chip Oscillator Clock This clock is supplied by a on-chip oscillator. There are two kinds of on-chip oscillator: high-speed on- chip oscillator and low-speed on-chip oscillator. These oscillators are selected by the bit HR01 bit in the ...
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R8C/13 Group 6.3 CPU Clock and Peripheral Function Clock There are two types of clocks: CPU clock to operate the CPU and peripheral function clock to operate the peripheral functions. Also refer to “Figure 6.1 Clock Generating Circuit”. 6.3.1 CPU ...
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R8C/13 Group 6.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as normal operation mode. 6.4.1 Normal Operation Mode Normal operation mode is further classified into four modes. In ...
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R8C/13 Group Table 6.2 Setting Clock Related Bit and Modes divided ...
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R8C/13 Group 6.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU and the watchdog timer because both are operated by the CPU clock. Because the main clock and on-chip oscillator clock both are ...
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R8C/13 Group 6.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount ...
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R8C/13 Group Figure 6.6 shows the state transition of power control. Low-speed On-chip Oscillator Mode High-speed Mode, Middle-speed mode OCD2=0 CM05=0 CM13=1 High-speed On-chip Oscillator Mode Interrupt WAIT Instruction Wait Mode Figure 6.6 State Transition of Power Control Rev.1.20 Jan ...
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R8C/13 Group 6.5 Oscillation Stop Detection Function The oscillation stop detection function is such that main clock oscillation circuit stop is detected. The oscillation stop detection function can be enabled and disabled by the OCD1 to OCD0 bits in the ...
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R8C/13 Group Table 6.5 Interrupt Factor Determination of Oscillation Stop Detection, Watchdog Timer Interrupt or Voltage Detection Interrupt Generated Interrupt Factor Oscillation stop detection ( (a) or (b) ) Watchdog timer Voltage detection Figure 6.7 Switching Clock Source From Low-speed ...
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R8C/13 Group 7. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 7.1 shows the PRCR register. The following lists the registers protected ...
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R8C/13 Group 8. Processor Mode 8.1 Types of Processor Mode The processor mode is single-chip mode. Table 8.1 shows the features of the processor mode. Figure 8.1 shows the PM0 and PM1 register. Table 8.1 Features of Processor Mode Processor ...
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R8C/13 Group 9. Bus During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for access space. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word ...
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R8C/13 Group 10. Interrupt 10.1 Interrupt Overview 10.1.1 Type of Interrupts Figure 10.1 shows types of interrupts. Software (Non-maskable interrupt) Interrupt Hardware NOTES: 1. Peripheral function interrupts are generated by the peripheral functions built in the microcomputer system. 2. Avoid ...
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R8C/13 Group 10.1.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non- maskable interrupts. • Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow Interrupt An overflow interrupt occurs ...
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R8C/13 Group 10.1.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function inter- rupts. (1) Special Interrupts Special interrupts are non-maskable interrupts. • Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog ...
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R8C/13 Group 10.1.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respec- tive interrupt vectors. When an interrupt request is accepted, the CPU branches to the address ...
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R8C/13 Group • Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 10.2 lists interrupts and vector tables located in the relocatable vector table. Table 10.2 ...
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R8C/13 Group 10.1.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the FLG register’s ...
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R8C/13 Group • I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. • IR Bit The ...
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R8C/13 Group • Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here interrupt occurs during execution ...
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R8C/13 Group • Interrupt Response Time Figure 10.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the inter- rupt routine ...
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R8C/13 Group • Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the ...
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R8C/13 Group • Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of ...
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R8C/13 Group • Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 10.9 shows the Interrupts Priority Select Circuit ...
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R8C/13 Group ______ 10.2 INT Interrupt ________ 10.2.1 INT0 Interrupt _______ INT0 interrupt is triggered by an INT0 input. When using INT0 interrupts, the INT0EN bit in the INTEN register must be set to “1” (enabling). The edge polarity is ...
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R8C/13 Group _______ 10.2.2 INT0 Input Filter _______ The INT0 input has a digital filter which can be sampled by one of three sampling clocks. The sampling clock is selected using the INT0F1 to INT0F0 bits in the INT0F register. ...
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R8C/13 Group ______ 10.2.3 INT1 Interrupt and INT2 Interrupt ______ INT1 interrupts are triggered by INT1 inputs. The edge polarity can be selected with the R0EDG bit in the TXMR register. The INT1 pin is shared with the CNTR0 pin. ...
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R8C/13 Group ______ 10.2.4 INT3 Interrupt _______ INT3 interrupts are triggered by INT3 inputs. The TCC07 bit in the TCC0 register should “0” _______ _______ (INT3). The INT3 input has a digital filter which can be sampled ...
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R8C/13 Group 10.3 Key Input Interrupt A key input interrupt is generated on an input edge of any of the K1 be used as a key-on wakeup function to exit wait or stop mode. KIi input can be enabled or ...
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R8C/13 Group 10.4 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0, 1). Set the start address of any instruction in the RMADi register. Use the ...
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R8C/13 Group Address match interrupt enable register Address match interrupt register (b19) (b16) (b15) (b23 Figure 10.17 AIER Register and RMAD0 to RMAD1 ...
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R8C/13 Group 11. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom- mend using the watchdog timer to improve reliability of a system. Figure 11.1 shows the watchdog timer ...
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R8C/13 Group 12. Timers The microcomputer has three 8-bit timers and one 16-bit timer. The three 8-bit timers are Timer X, Timer Y, and Timer Z and each one has an 8-bit prescaler. The 16-bit timer is Timer C and ...
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R8C/13 Group 12.1 Timer X The Timer 8-bit timer with an 8-bit prescaler. Figure 12.1 shows the block diagram of Timer X. Figures 12.2 and 12.3 show the Timer X-related registers. The Timer X has five operation ...
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R8C/13 Group Prescaler X Register b7 Timer X Register ...
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R8C/13 Group 12.1.1 Timer Mode In this mode, the timer counts an internally generated count source (See “Table 12.2 Timer Mode Specifications”). Figure 12.4 shows the TXMR register in timer mode. Table 12.2 Timer Mode Specifications Item Count source f ...
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R8C/13 Group 12.1.2 Pulse Output Mode In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin a pulse whose polarity is inverted each time the timer underflows (See “Table 12.3 Pulse Output mode ...
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R8C/13 Group 12.1.3 Event Counter Mode In this mode, the timer counts an external signal fed to INT1/CNTR Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode. Table 12.4 Event Counter Mode Specifications Item Count source External ...
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R8C/13 Group 12.1.4 Pulse Width Measurement Mode In this mode, the timer measures the pulse width of an external signal fed to INT1/CNTR0 pin (See “Table 12.5 Pulse Width Measurement Mode Specifications”). Figure 12.7 shows the TXMR register in pulse ...
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R8C/13 Group n = high-level: the contents of TX register, low-level: the contents of PREX register FFFF 16 Count start n 0000 16 Set to "1" by program “1” TXS bit in TXMR register “0” “H” Measurement pulse (CNTR0 pin ...
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R8C/13 Group 12.1.5 Pulse Period Measurement Mode In this mode, the timer measures the pulse period of an external signal fed to INT1/CNTR0 pin (See “Table 12.6 Pulse Period Measurement Mode Specifications”). Figure 12.9 shows the TXMR register in pulse ...
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R8C/13 Group 12.2 Timer Y Timer 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Y Primary and Timer Y Secondary. Figure 12.11 shows a block diagram of Timer Y. Figures 12.12 to 12.14 show ...
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R8C/13 Group 12.2.1 Timer Mode In this mode, the timer counts an internally generated count source (see “Table 12.7 Timer Mode Specifications”). An external signal input to the CNTR1 pin can be counted. The TYSC register is unused in timer ...
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R8C/13 Group 12.2.2 Programmable Waveform Generation Mode In this mode, an signal output from the TY the values in the TYPR register and TYSC register are counted alternately (see “Table 12.8 Program- mable Waveform Generation Mode Specifications”). A counting starts ...
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R8C/13 Group "1" TYS bit in TYZMR register "0" Count starts Count source Prescaler Y underflow signal Contents of Timer Y "1" IR bit in TYIC register "0" "1" TYOPL bit in PUM register "0" "H" CNTR1 pin output "L" ...
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R8C/13 Group 12.3 Timer Z Timer 8-bit timer with an 8-bit prescaler and has two reload registers-Timer Z Primary and Timer Z Secondary. Figure 12.18 shows a block diagram of Timer Z. Figures 12.19 to 12.21 show ...
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R8C/13 Group 12.3.1 Timer Mode In this mode, the timer counts an internally generated count source or Timer Y underflow (see “Table 12.9 Timer Mode Specifications”). The TZSC register is unused in timer mode. Figure 12.22 shows the TYZMR register ...
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R8C/13 Group 12.3.2 Programmable Waveform Generation Mode In this mode, an signal output from the TZ the values in the TZPR register and TZSC register are counted alternately (see “Table 12.10 Program- mable Waveform Generation Mode Specifications”). A counting starts ...
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R8C/13 Group 12.3.3 Programmable One-shot Generation Mode In this mode, upon program command or external trigger input (input to the INT0 pin), the microcom- puter outputs the one-shot pulse from the TZ Generation Mode Specifications”). When a trigger occurs, the ...
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R8C/13 Group “1” TZS bit in TYZMR register “0” Set to “1” TZOS bit in TYZOC register “0” Count source Prescaler Z underflow signal “1” INT pin input 0 “0” Contents of Timer Z “1” IR bit in TZIC register ...
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R8C/13 Group 12.3.4 Programmable Wait One-shot Generation Mode In this mode, upon program or external trigger input (input to the INT0 pin), the microcomputer outputs the one-shot pulse from the TZ Programmable Wait One-shot Generation Mode Specifications”). When a trigger ...
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R8C/13 Group “1” TZS bit in TYZMR register “0” Set to trigger “1” TZOS bit in TYZOC register “0” Count source Prescaler Z underflow signal “1” INT input pin 0 “0” Contents of Timer Z “1” IR bit in TZIC ...
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R8C/13 Group 12.4 Timer C Timer 16-bit timer. Figure 12.28 shows a block diagram of Timer C. Figure 12.29 shows a block diagram of CMPs waveform generation unit. Figure 12.30 shows a block diagram of CMP waveform ...
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R8C/13 Group TCC14 TCC15 Compare 0 interrupt signal Compare 1 interrupt signal TCC16 TCC17 TCC17 to TCC16 H =11 L =10 Reverse =01 TCC15 to TCC14 Reverse =01 L =10 H =11 TCC14 to TCC17: Bits in TCC1 register Figure ...
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R8C/13 Group Timer C register (b15) (b8 Capture and compare 0 register (b15) (b8 Output compare NOTES: 1. When setting a value in the TM0 register, set the TCC13 bit in the TCC1 register ...
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R8C/13 Group 12.4.1 Input Capture Mode This mode uses an edge input to TC generates an interrupt request. The TC noise from occurring. Table 12.13 shows specifications in input capture mode. Figure 12.33 shows an operation example ...
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R8C/13 Group FFFF 16 Count start 0000 16 Set to "1" by program “1” TCC00 bit in TCC0 register “0” Measurement pulse “H” (TC pin input) IN “L” Transmit timing from Timer C counter to TM0 register Indeterminate TM0 register ...
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R8C/13 Group 12.4.2 Output Compare Mode In this mode, an interrupt request is generated when the value of TC register matches the value of TM0 or TM1 register. Table 12.14 shows specifications in output compare mode. Figure 12.34 shows an ...
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R8C/13 Group 13. Serial Interface Serial interface is configured with two channels: UART0 to UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 13.1 shows a block ...
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R8C/13 Group PAR 1SP Figure 13.2 UARTi Transmit/Receive Unit Rev.1.20 Jan 27, 2006 page 110 of ...
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R8C/13 Group UARTi transmit/receive control register 1 (i= ...
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R8C/13 Group 13.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. This mode can be selected with UART0. Table 13.1 lists the specifications of the clock synchronous serial ...
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R8C/13 Group Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Bit U0TB U0RB OER U0BRG U0MR SMD2 to SMD0 CKDIR U0C0 CLK1 to ...
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R8C/13 Group • Example of transmit timing (when internal clock is selected) Transfer clock “1” U0C1 register TE bit Write data to U0TB register “0” U0C1 register “1” TI bit “0” CLK 0 TxD U0C0 ...
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R8C/13 Group 13.1.1 Polarity Select Function Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity ...
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R8C/13 Group 13.1.3 Continuous Receive Mode Continuous receive mode is held by setting setting the U0RRM bit in the UCON register to “1” (en- ables continuous receive mode). In this mode, reading the U0RB register sets the TI bit in ...
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R8C/13 Group 13.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the ...
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R8C/13 Group Table 13.5 Registers to Be Used and Settings in UART Mode Register Bit UiTB UiRB OER,FER,PER,SUM Error flag UiBRG UiMR SMD2 to SMD0 CKDIR STPS PRY, PRYE UiC0 CLK0, ...
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R8C/13 Group • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock UiC1 register “1” TE bit Write data to UiTB register “0” “1” UiC1 register TI bit “0” Start bit ...
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R8C/13 Group • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG output “1” UiC1 register RE bit “0” RxDi Transfer clock Reception triggered when transfer clock “1” UiC1 register is generated ...
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R8C/13 Group 13.2.3 Bit Rate Divided-by-16 of frequency by the UiBRG (i register in UART mode is a bit rate. <UART Mode> • When selecting internal clock Setting value to the UiBRG register = fj : Count source ...
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R8C/13 Group 14. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog inputs share the pins with P0 using these pins, make sure the corresponding port direction bits ...
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R8C/13 Group 14.1 One-shot Mode In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 14.2 lists the specifications of one-shot mode. Figure 14.4 shows the ADCON0 and ADCON1 registers in one- shot mode. Table ...
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R8C/13 Group 14.2 Repeat Mode In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 14.3 lists the specifications of repeat mode. Figure 14.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 14.3 ...
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R8C/13 Group 14.3 Sample and Hold If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin is increased to 28 and-hold is effective in all operation modes. Select whether or not ...
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R8C/13 Group 14.5 Internal Equivalent Circuit of Analog Input Figure 14.8 shows the internal equivalent circuit of analog input Parasitic diode ON resistor approx. 2k AN0 SW1 Parasitic diode i ladder-type V SS switches ...
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R8C/13 Group 14.6 Inflow Current Bypass Circuit Figure 14.9 shows the configuration of the inflow current bypass circuit, figure 14.10 shows the ex- ample of an inflow current bypass circuit where V Unselected channel Selected channel Figure 14.9 Configuration of ...
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R8C/13 Group 14.7 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.11 has to be completed within a specified period of time. T (sampling time) as the ...
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R8C/13 Group VIN Figure 14.11 Analog Input Pin and External Sensor Equivalent ...
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R8C/13 Group 15. Programmable I/O Ports 15. 1 Description The programmable input/output ports (hereafter referred to as “I/O ports”) consist of 22 lines P0, P1 and P4 . Each port can be set for ...
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R8C/13 Group 15.2 Port setting Table 15.1 to Table 15.23 list the port setting. Table 15.1 Port P0 / Register PD0 PUR0 CH2, CH1, CH0, Bit PD0_0 PU00 Setting ...
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R8C/13 Group Table 15.5 Port P0 /AN Setting 4 3 Register PD0 PUR0 Bit PD0_4 PU01 Setting value “0” or “1” Table 15.6 Port P0 /AN setting 5 2 Register PD0 ...
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R8C/13 Group _____ Table 15.10 Port P1 /KI / Register PD1 PUR0 DRR Bit PD1_1 PU02 DRR1 Setting value “0” or ...
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R8C/13 Group Table 15.13 Port Setting Register PD1 PUR0 Bit PD1_4 PU03 DRR4 Setting value “0” or ...
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R8C/13 Group _______ Table 15.16 Port P1 /INT /CNTR 7 1 Register PD1 PUR0 Bit PD1_7 PU03 DRR5 Setting value “0” or “1” ___________ Table ...
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R8C/13 Group Table 15.20 Port P3 /INT / Register PD3 PUR0 Bit PD3_3 PU06 Setting value “0” or “1” Table 15.21 Port ...
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R8C/13 Group 15.3 Unassigned Pin Handling Table 15.24 lists the handling of unassigned pins. Table 15.24 Unassigned Pin Handling • ...
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R8C/13 Group 16. Electrical Characteristics Table 16.1 Absolute Maximum Ratings Symbol Parameter V Supply voltage CC AV Analog supply voltage CC Input voltage Output voltage O P Power dissipation d T Operating ambient temperature opr Storage temperature ...
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R8C/13 Group Table 16.3 A/D Conversion Characteristics Symbol Parameter – – ...
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R8C/13 Group Table 16.4 Flash Memory (Program ROM) Electrical Characteristics – ...
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R8C/13 Group Table 16.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics Symbol – ...
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R8C/13 Group Table 16.6 Voltage Detection Circuit Electrical Characteristics Symbol Parameter Voltage detection level Vdet Voltage detection interrupt request generating time Voltage detection circuit self consumption current td(E-A) Waiting time until voltage detection circuit operation starts Microcomputer operation voltage minimum ...
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R8C/13 Group Table 16.9 High-speed On-Chip Oscillator Circuit Electrical Characteristics ...
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R8C/13 Group Table 16.12 Electrical Characteristics ( ...
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R8C/13 Group Timing requirements [V CC Table 16.13 X input IN Symbol input cycle time input HIGH pulse width input LOW pulse ...
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R8C/13 Group CNTR0 input TCIN input X input IN CLK i TxD i RxD i INT i Figure 16.4 Vcc=5V timing diagram Rev.1.20 Jan 27, 2006 page 160 of 205 REJ09B0111-0120 t c(CNTR0) t WH(CNTR0) t WL(CNTR0) t c(TCIN) t ...
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R8C/13 Group Table 16.18 Electrical Characteristics ( " H " ...
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R8C/13 Group Table 16.19 Electrical Characteristics ( Parameter ...
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R8C/13 Group Timing requirements [V CC Table 16.20 X input IN Symbol input cycle time input HIGH pulse width input LOW pulse ...
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R8C/13 Group CNTR0 input TCIN input X input IN CLK i TxD i RxD i INT i Figure 16.5 Vcc=3V timing diagram Rev.1.20 Jan 27, 2006 page 164 of 205 REJ09B0111-0120 t c(CNTR0) t WH(CNTR0) t WL(CNTR0) t c(TCIN) t ...
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R8C/13 Group 17. Flash Memory Version 17.1 Overview The flash memory version has two modes—CPU rewrite and standard serial I/O—in which its flash memory can be operated on. Table 17.1 outlines the performance of flash memory version (see “Table 1.1 ...
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R8C/13 Group 17.2 Memory Map The ROM in the flash memory version is separated between a user ROM area and a boot ROM area (reserved area). Figure 17.1 shows the block diagram of flash memory. The user ROM area has ...
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R8C/13 Group 17.3 Functions To Prevent Flash Memory from Rewriting To prevent the flash memory from being read or rewritten easily, standard serial I/O mode has an ID code check function. 17.3.1 ID Code Check Function Use this function in ...
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R8C/13 Group 17.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on- board ...
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R8C/13 Group 17.4.1 EW0 Mode The microcomputer is placed in CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11 ...
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R8C/13 Group Figure 17.3 shows the FMR0 register. Figure 17.4 shows the FMR1 and FMR4 registers. • FMR00 Bit This bit indicates the operating status of the flash memory. The bit is “0” during programming, eras- ing, or erase-suspend mode; ...
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R8C/13 Group • FMR40 bit The erase-suspend function is enabled by setting the FMR40 bit to “1” (valid). • FMR41 bit In EW0 mode, the flash module goes to erase-suspend mode when the FMR41 bit is set to “1”. In ...
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R8C/13 Group Figures 17.5 shows the timing on suspend operation. Erase Starts During Erase FMR00 FMR46 Figure 17.5 Timing on Suspend Operation Figures 17.6 and 17.7 show the setting and resetting of EW0 mode and EW1 mode, respectively ...
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R8C/13 Group 17.4.3 Software Commands Software commands are described below. The command code and data must be read and written in 8-bit units. Table 17.4 Software Commands Command Read array Read status register Clear status register Program Block erase SRD: ...
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R8C/13 Group • Program Command This command writes data to the flash memory in one byte units. Write ‘40 ’ in the first bus cycle and write data to the write address in the second bus cycle, and an 16 ...
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R8C/13 Group • Block Erase Write ‘20 ’ in the first bus cycle and write ‘D0 16 cycle, and an auto erase operation (erase and verify) will start. Check the FMR00 bit in the FMR0 register to see if auto ...
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R8C/13 Group 17.4.4 Status Register The status register indicates the operating status of the flash memory and whether an erase or pro- gramming operation terminated normally or in error. The status of the status register can be known by reading ...
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R8C/13 Group 17.4.5 Full Status Check When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur- rence of each specific error. Therefore, execution results can be verified by checking these status ...
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R8C/13 Group 17.5 Standard Serial I/O Mode In standard serial I/O mode, the user ROM area can be rewritten while the microcomputer is mounted on- board by using a serial programmer suitable for this microcomputer. Standard serial I/O mode has ...
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R8C/13 Group Table 17.7 Pin Functions (Flash Memory Standard Serial I/O Mode ...
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R8C/13 Group • Example of Circuit Application in the Standard Serial I/O Mode Figures 17.14 and 17.15 show examples of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the serial programmer manual of your ...
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R8C/13 Group 18. On-chip debugger The microcomputer has functions to execute the on-chip debugger. Refer to "Appendix 2 Connecting examples for serial writer and on-chip debugging emulator". Refer to the respective on-chip debugger manual for the details of the on-chip ...
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R8C/13 Group 19. Usage Notes 19.1 Stop Mode and Wait Mode 19.1.1 Stop Mode When entering stop mode, set the CM10 bit to “1” (stop mode) after setting the FMR01 bit to “0” (CPU rewrite mode disabled). The instruction queue ...
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R8C/13 Group 19.2 Interrupt 19.2.1 Reading Address 00000 Do not read the address 00000 the CPU reads interrupt information (interrupt number and interrupt request level) from 00000 interrupt sequence. At this time, the acknowledged interrupt IR bit is set to ...
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R8C/13 Group 19.2.5 Changing Interrupt Factor The IR bit in the interrupt control register may be set to “1” (interrupt requested) when the interrupt factor is changed. When using an interrupt, set the IR bit to “0” (interrupt not request) ...