DSPIC33FJ128GP206 MICROCHIP [Microchip Technology], DSPIC33FJ128GP206 Datasheet

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DSPIC33FJ128GP206

Manufacturer Part Number
DSPIC33FJ128GP206
Description
Silicon Errata
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet

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dsPIC33FJXXXGPXXX,
dsPIC33FJXXXMCXXX
(Rev. A2) Silicon Errata
The dsPIC33F devices (Rev. A2) you received were
found to conform to the specifications and functionality
described in the following documents:
• DS70165 – “dsPIC33F Family Data Sheet”
• DS70157 – “dsPIC30F/33F Programmer’s
• DS70046 – “dsPIC30F Family Reference Manual”
The exceptions to the specifications in the documents
listed above are described in this section. The specific
devices for which these exceptions are described are
listed below:
• dsPIC33FJ64GP206
• dsPIC33FJ64GP306
• dsPIC33FJ64GP310
• dsPIC33FJ64GP706
• dsPIC33FJ64GP708
• dsPIC33FJ64GP710
• dsPIC33FJ128GP206
• dsPIC33FJ128GP306
• dsPIC33FJ128GP310
• dsPIC33FJ128GP706
• dsPIC33FJ128GP708
• dsPIC33FJ128GP710
• dsPIC33FJ256GP506
• dsPIC33FJ256GP510
• dsPIC33FJ256GP710
• dsPIC33FJ64MC506
• dsPIC33FJ64MC508
• dsPIC33FJ64MC510
• dsPIC33FJ64MC706
• dsPIC33FJ64MC710
• dsPIC33FJ128MC506
• dsPIC33FJ128MC510
• dsPIC33FJ128MC706
• dsPIC33FJ128MC708
• dsPIC33FJ128MC710
• dsPIC33FJ256MC510
• dsPIC33FJ256MC710
© 2006 Microchip Technology Inc.
Reference Manual”
dsPIC33F Rev. A2 Silicon Errata
dsPIC33FJXXXGPXXX/
dsPIC33FJXXXMCXXX
dsPIC33F Rev. A2 silicon is identified by performing a
“Reset and Connect” operation to the device using
MPLAB
output window will show a successful connection to the
device specified in Configure>Select Device.
The errata described in this section will be addressed
in future revisions of silicon.
Silicon Errata Summary
The following list summarizes the errata described in
further detail through the remainder of this document:
1.
2.
3.
4.
5.
6.
Doze Mode
When Doze mode is enabled, any writes to a
peripheral SFR can cause other updates to that
register to cease to function for the duration of the
current CPU clock cycle.
12-bit Analog-to-Digital Converter (ADC) Module
For this revision of silicon, the 12-bit ADC module
INL, DNL and signal acquisition time parameters
are not within the published data sheet
specifications.
10-bit ADC Module
For this revision of silicon, the 10-bit ADC module
DNL, conversion speed and signal acquisition time
parameters are not within the published data sheet
specifications.
DMA Module: Interaction with EXCH Instruction
The EXCH instruction does not execute correctly
when one of the operands contains a value equal
to the address of the DMAC SFRs.
DISI Instruction
The DISI instruction will not disable interrupts if a
DISI instruction is executed in the same instruc-
tion cycle that the DISI counter decrements to
zero.
Motor Control PWM
There is a glitch in the PWMxL signal in Single-
Shot mode with complementary output. Another
glitch occurs when resuming from a Fault condition
in Free-Running mode with complementary
output.
®
ICD 2 with MPLAB IDE v7.40 or later. The
DS80279B-page 1

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DSPIC33FJ128GP206 Summary of contents

Page 1

... The specific devices for which these exceptions are described are listed below: • dsPIC33FJ64GP206 • dsPIC33FJ64GP306 • dsPIC33FJ64GP310 • dsPIC33FJ64GP706 • dsPIC33FJ64GP708 • dsPIC33FJ64GP710 • dsPIC33FJ128GP206 • dsPIC33FJ128GP306 • dsPIC33FJ128GP310 • dsPIC33FJ128GP706 • dsPIC33FJ128GP708 • dsPIC33FJ128GP710 • dsPIC33FJ256GP506 • dsPIC33FJ256GP510 • dsPIC33FJ256GP710 • ...

Page 2

Output Compare Module The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. 8. Output ...

Page 3

Module: 12-bit ADC When the ADC module is configured for 12-bit operation, the specifications in the data sheets are not met. Work around Implement the ADC module as an 11-bit ADC with a maximum conversion rate of 300 Ksps. ...

Page 4

Module: 10-bit ADC When the ADC module is configured for 10-bit operation, the specifications in the data sheet are not met for operation above 500 Ksps. For 500 Ksps, the module meets specifications except for Gain and Offset ...

Page 5

Module: DISI Instruction When a user executes a DISI #7, for example, this will disable interrupts for cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down ...

Page 6

Module: SPI Module in Frame Master Mode The SPI module will fail to generate frame syn- chronization pulses when configured in the Frame Master mode (FRMEN = 1, SPIFSD = 0). How- ever, the module functions correctly in ...

Page 7

Module: INT0, ADC and Sleep/Idle Mode ADC event triggers from the INT0 pin will not wake-up the device from Sleep or Idle mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate ...

Page 8

APPENDIX A: REVISION HISTORY Revision A (6/2006) • Initial release of the document. Revision B (12/2006) • Added errata 10, 11, 12, 13, 14, 15, 16 and 17. DS80279B-page 8 © 2006 Microchip Technology Inc. ...

Page 9

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families ...

Page 10

W ORLDWIDE AMERICAS ASIA/PACIFIC Corporate Office Asia Pacific Office 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Chandler, AZ 85224-6199 Tower 6, The Gateway Tel: 480-792-7200 Habour City, Kowloon Fax: 480-792-7277 Hong Kong Technical Support: Tel: 852-2401-1200 http://support.microchip.com Fax: 852-2401-3431 ...

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