R5F21346ZJFP RENESAS [Renesas Technology Corp], R5F21346ZJFP Datasheet - Page 22

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R5F21346ZJFP

Manufacturer Part Number
R5F21346ZJFP
Description
RENESAS MCU
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Under development
R8C/34W Group, R8C/34X Group, R8C/34Y Group, R8C/34Z Group
REJ03B0312-0010 Rev.0.10
Apr 09, 2010
2.8.7
2.8.8
2.8.9
2.8.10
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
If necessary, set to 0. When read, the content is undefined.
Interrupt Enable Flag (I)
Stack Pointer Select Flag (U)
Processor Interrupt Priority Level (IPL)
Reserved Bit
Preliminary document
Specifications in this document are tentative and subject to change.
2. Central Processing Unit (CPU)
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