M30622ECTFP

Manufacturer Part NumberM30622ECTFP
DescriptionSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ManufacturerMITSUBISHI [Mitsubishi Electric Semiconductor]
M30622ECTFP datasheet
 


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Description
Description
The M16C/62T group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin or a 80-pin plastic
molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high
level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at
high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office,
communications, industrial equipment, and other high-speed processing applications.
The M16C/62T group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity ..................................M30623M4T-XXXGP : ROM 32K bytes, RAM 3K bytes
• Shortest instruction execution time ......62.5ns (f(X
• Supply voltage ..................................... Mask ROM version : 4.2 to 5.5V (f(X
• Low power consumption ......................140mW (V
• Interrupts
• Multifunction 16-bit timer ......................5 I/O timers + 6 input timers(M30622(100-pin package))
• Inside 16-bit timer ................................ 3 timers(only M30623(80-pin package))(Note 1)
• Serial I/O .............................................. • M30622(100-pin package) : 3 for UART or clock synchronous + 2 for synchronous
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 10 bits X 8 channels (Expandable up to 26 channels)
• D-A converter ....................................... 8 bits X 2 channels
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer ....................................1 line
• Programmable I/O ...............................87 lines(M30622(100-pin package)),70 lines(M30623(80-pin package))
• Input port..............................................
• Memory expansion .............................. Available (to 1.2M bytes or 4M bytes)
• Chip select output ................................ 4 lines(only M30622(100-pin package))(Note 2)
• Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator)
Note 1: In M30623(80-pin package), these timers have no corresponding external pin can be used as
internal timers.
Note 2: M30623(80-pin package) has no external pin for chip select output.
Applications
Audio, cameras, office equipment, communications
equipment, portable equipment, cars, etc
Central Processing Unit (CPU) ..................... 12
Reset ............................................................. 15
Processor Mode ............................................ 28
Clock Generating Circuit ............................... 40
Protection ...................................................... 49
Interrupts ....................................................... 50
Watchdog Timer ............................................ 70
DMAC ........................................................... 72
M30622M8T/M8V-XXXFP,M30623M8T/M8V-XXXGP : ROM 64K bytes, RAM 4K bytes
M30622MCT/MCV-XXXFP,M30623MCT/MCV-XXXGP : ROM 128K bytes, RAM 5K bytes
M30622ECT/ECV-XXXFP,M30623ECT/ECV-XXXGP : PROM 128K bytes, RAM 5K bytes
)=16MH
, V
IN
Z
CC
One-time PROM version : 4.5 to 5.5V (f(X
= 5V, f(X
)=16MH
CC
IN
25 internal interrupt sources, 8 external interrupt sources (M30622(100-pin package))
/5 sources (M30623(80-pin package)), 4 software interrupt sources,
7 levels (including key input interrupt)
3 I/O timers + 5 input timers(M30623(80-pin package))
• M30623(80-pin package) : 3 for UART or clock synchronous(one of exclusive UART)
+ 2 for synchronous(one of exclusive transmission)
_______
1 line (P8
shared with NMI pin)
5
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error.
Specifications in this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
------Table of Contents------
Timer ............................................................. 82
Timers’ function for three-phase motor control.......... 100
Serial I/O ..................................................... 112
A-D Converter ............................................. 146
D-A Converter ............................................. 157
CRC Calculation Circuit .............................. 159
Programmable I/O Ports ............................. 161
Electrical characteristics ............................. 176
1
Mitsubishi microcomputers
M16C / 62T Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
=5V)
)=16MH
, without software wait)
IN
Z
)=16MH
, without software wait)
IN
Z
)
Z

M30622ECTFP Summary of contents

  • Page 1

    Description Description The M16C/62T group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin or a 80-pin plastic molded QFP. These single-chip microcomputers operate using ...

  • Page 2

    Description Pin Configuration Figures 1.1.1 show the pin configurations (top view) of M30622(100-pin package) and 1.1.2 show the pin configurations (top view) of M30623(80-pin package). PIN CONFIGURATION (top view ...

  • Page 3

    Description PIN CONFIGURATION (top view ...

  • Page 4

    Description Block Diagram Figure 1.1.3 is block diagrams of M30622(100-pin package) and 1.1.4 is block diagrams of M30623(80-pin package). Port P0 I/O ports Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer ...

  • Page 5

    Description Port P0 I/O ports Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 ...

  • Page 6

    Description Performance Outline Table 1.1 performance outline of M16C/62T group. Table 1.1.1. Performance outline of M16C/62T group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0, P2, P3, P5, P6, P10 ...

  • Page 7

    ... Mask ROM version Note 1: It may change in the future. Note 2: Use shipped in blank of one-time PROM version as the trial, development of program. In case of vehicle-mount test or mass production, use shipped in programming. Figure 1.1.5. ROM expansion 100-pin packaege M30622ECT-XXXFP M30622ECTFP M30623MCT-XXXGP M30622ECV-XXXFP M30623MCV-XXXGP M30622ECVFP M30623M8T-XXXGP M30623M8V-XXXGP ...

  • Page 8

    ... Description The M16C/62T group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62T group ROM Type No. capacity M30622M8T-XXXFP 64K bytes M30622M8V-XXXFP M30622MCT-XXXFP M30622ECT-XXXFP M30622ECTFP 128K bytes M30622MCV-XXXFP M30622ECV-XXXFP M30622ECVFP M30623M4T-XXXGP 32K bytes 3K bytes M30623M8T-XXXGP 64K bytes 4K bytes M30623M8V-XXXGP M30623MCT-XXXGP M30623ECT-XXXGP M30623ECTGP 128K bytes ...

  • Page 9

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Pin Description Pin Description Pin name Signal name Power supply CC SS input CNV CNV SS SS ____________ RESET Reset input X Clock ...

  • Page 10

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Pin Description Pin Description Pin name Signal name I/O port ______ ______ ...

  • Page 11

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Operation of Functional Blocks The M16C/62T group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data ...

  • Page 12

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, ...

  • Page 13

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) ...

  • Page 14

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. CPU • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) ...

  • Page 15

    Reset Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is ...

  • Page 16

    Reset Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. Table 1.6.1. Pin status when RESET ...

  • Page 17

    Reset (1) Processor mode register 0 (Note 1) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) ...

  • Page 18

    Reset (51) SI/O3 control register (52) SI/O4 control register (53) UART2 special mode register (54) UART2 transmit/receive mode register (55) UART2 transmit/receive control register 0 (56) UART2 transmit/receive control register 1 (57) Count start flag (58) Clock prescaler reset flag ...

  • Page 19

    SFR 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 (PM0) 0004 16 Processor mode register 1(PM1) 0005 16 System clock control register 0 (CM0) 0006 16 System clock control register 1 (CM1) 0007 16 Chip select ...

  • Page 20

    SFR 0340 Timer B3 count start flag (TBSR) 16 0341 16 0342 16 Timer A1-1 register (TA11) 0343 16 0344 16 Timer A2-1 register (TA21) 0345 16 0346 16 Timer A4-1 register (TA41) 0347 16 Three-phase PWM control ...

  • Page 21

    SFR Figure 1.7.3. Location of peripheral unit control registers (3) 03C0 16 A-D register 0 (AD0) 03C1 16 03C2 16 A-D register 1 (AD1) 03C3 16 03C4 16 A-D register 2 (AD2) 03C5 16 03C6 16 A-D register 3 (AD3) ...

  • Page 22

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions Memory Space Expansion Features Here follows the description of the memory space expansion function. With the processor running in memory expansion mode ...

  • Page 23

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions (2) Expansion mode 1 In this mode, the memory space can be expanded by 176K bytes in addition to that in normal ...

  • Page 24

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions A connection example Figure 1.8.3 shows a connection example of the MCU with the external memories in expansion mode 1. _______ In ...

  • Page 25

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions (3) Expansion mode 2 In expansion mode 2, the data bank register (0000B register. Data bank register ...

  • Page 26

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). ...

  • Page 27

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Memory Space Expansion Functions Areas used for data only 000000 16 to 380000 16 Area commonly used for data and programs 380000 to 3BFFFF 16 16 ...

  • Page 28

    Software Reset Software Reset Writing “1” to bit 3 of the processor mode register 0 (address 0004 microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) ...

  • Page 29

    Processor Mode Processor mode register 0 (Note Note 1: Set bit 1 of the protect register (address 000A Note 2: If the V CC (PM00 and PM01 both are set to ...

  • Page 30

    Processor Mode Single-chip mode 00000 16 SFR area 00400 16 Internal RAM area XXXXX 16 04000 16 Inhibited D0000 16 YYYYY 16 Internal ROM area FFFFF 16 Type No. M30623M4T-XXXGP M30622M8T/M8V-XXXFP M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP M30623MCT/MCV-XXXGP Figure 1.10.1. Memory maps in each ...

  • Page 31

    Bus Settings Bus Settings The BYTE pin and bits the processor mode register 0 (address 0004 settings. In M30623(80-pin package), the BYTE signal has no external pin, and is internally connected to the CNV signal. Accordingly, ...

  • Page 32

    Bus Settings Table 1.11.2. Pin functions for each processor mode Single-chip Processor mode mode Multiplexed bus space select bit Data bus width BYTE pin level I/O port I/O port ...

  • Page 33

    Bus Control Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. ...

  • Page 34

    Bus Control Chip select control register Note: In M30623(80-pin package), the chip select signals has no corresponding Figure 1.12.1. Chip select control register (3) Read/write signals With a 16-bit data bus (BYTE ...

  • Page 35

    Bus Control (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = “H” ALE Address ...

  • Page 36

    Bus Control In an instance of separate bus BCLK (Note) RDY In an instance of multiplexed bus BCLK (Note) RDY : Wait using RDY signal : Wait using ...

  • Page 37

    Bus Control (7) External bus status when the internal area is accessed Table 1.12.6 shows the external bus status when the internal area is accessed. Table 1.12.6. External bus status when the internal area is accessed Item Address bus Data ...

  • Page 38

    Bus Control (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 ) (Note) and bits the chip select control register (address ...

  • Page 39

    Bus Control < Separate bus (no wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Separate bus (with wait) > BCLK Write signal Read signal Data bus Address bus Chip select < Multiplexed bus > ...

  • Page 40

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock Generating Circuit Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral ...

  • Page 41

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock Generating Circuit Clock Control Figure 1.13.3 shows the block diagram of the clock generating circuit. CM10 “1” Write signal RESET Software reset NMI Interrupt request ...

  • Page 42

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main ...

  • Page 43

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock Generating Circuit Figure 1.13.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note ...

  • Page 44

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock Generating Circuit Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 output from ...

  • Page 45

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Wait Mode Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but ...

  • Page 46

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Status Transition of BCLK Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13.4 ...

  • Page 47

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Power control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal ...

  • Page 48

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Power control Transition of stop mode, wait mode All oscillators stopped Stop mode Interrupt All oscillators stopped Stop mode All oscillators stopped Stop mode Transition of ...

  • Page 49

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Protection Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of ...

  • Page 50

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Overview of Interrupt Type of Interrupts Figure 1.14.1 lists the types of interrupts. Software Interrupt Hardware Note: Peripheral I/O interrupts are generated by the peripheral ...

  • Page 51

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when ...

  • Page 52

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • ...

  • Page 53

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set ...

  • Page 54

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the ...

  • Page 55

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is ...

  • Page 56

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Interrupt control register Note 1: This bit can only be accessed for reset (= 0), but cannot ...

  • Page 57

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables ...

  • Page 58

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Rewrite the interrupt control register To rewrite the interrupt control register point that does not generate the interrupt request for that ...

  • Page 59

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine ...

  • Page 60

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time ( ...

  • Page 61

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the ...

  • Page 62

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of ...

  • Page 63

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as ...

  • Page 64

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Interrupt Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 ...

  • Page 65

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. ______ INT Interrupt ______ INT Interrupt ________ ________ INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the ...

  • Page 66

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. _______ NMI Interrupt ______ NMI Interrupt ______ An NMI interrupt is generated when the input to the non-maskable external interrupt. The pin level ...

  • Page 67

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Address Match Interrupt Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two ...

  • Page 68

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Precautions for Interrupts Precautions for Interrupts (1) Reading address 00000 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt ...

  • Page 69

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Precautions for Interrupts Figure 1.14.13. Switching condition of INT interrupt request (5) Rewrite the interrupt control register • To rewrite the interrupt control register ...

  • Page 70

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter ...

  • Page 71

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Watchdog Timer Watchdog timer control register Watchdog timer start register b7 Figure 1.15.2. Watchdog timer control ...

  • Page 72

    DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right ...

  • Page 73

    DMAC Table 1.16.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred DMA request factors (Note) Channel priority Transfer unit Transfer address direction Transfer mode DMA interrupt request generation timing When an underflow occurs in ...

  • Page 74

    DMAC DMA0 request cause select register Figure 1.16.2. DMAC register (1) Symbol Address DM0SL 03B8 16 Bit name Bit symbol DMA request cause DSEL0 select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. ...

  • Page 75

    DMAC DMA1 request cause select register DMAi control register Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit ...

  • Page 76

    DMAC DMAi source pointer ( (b19) (b16)(b15) (b23 DMAi destination pointer ( (b19) (b16) (b15) (b23 DMAi transfer counter ( (b15) (b8) b7 ...

  • Page 77

    DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to ...

  • Page 78

    DMAC (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address CPU use bus RD signal WR signal Data CPU use bus (2) 16-bit transfers and the source address is odd Transferring 16-bit data ...

  • Page 79

    DMAC (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.16.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of ...

  • Page 80

    DMAC DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one ...

  • Page 81

    DMAC (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA ...

  • Page 82

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function ...

  • Page 83

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer C32 TB0 IN TB1 IN TB2 IN TB3 IN TB4 IN TB5 IN Note 1: ...

  • Page 84

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A Timer A Figure 1.17.3 shows the block diagram of timer A. Figures 1.17.4 to 1.17.6 show the timer A-related registers. Except in event counter ...

  • Page 85

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A Timer Ai register (Note) (b15) b7 Count start flag Up/down flag Figure 1.17.5. Timer A-related registers (2) Symbol ...

  • Page 86

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A One-shot start flag Trigger select register Clock prescaler reset ...

  • Page 87

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.1.) Figure 1.17.7 shows the timer Ai mode ...

  • Page 88

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count ...

  • Page 89

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A Table 1.17.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source • Two-phase ...

  • Page 90

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A Timer Ai mode register (When not using two-phase pulse signal processing Note 1: ...

  • Page 91

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.17.4.) When a trigger occurs, the timer starts up and ...

  • Page 92

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.5.) In this ...

  • Page 93

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer A Condition : Reload register = 0003 (rising edge of TA Count source “H” TA pin iIN input signal “L” “H” PWM pulse output from ...

  • Page 94

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B Timer B Figure 1.17.14 shows the block diagram of timer B. Figures 1.17.15 and 1.17.16 show the timer B-related registers. Use the timer Bi ...

  • Page 95

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B Timer Bi register (Note) (b15) (b8 Count start flag Timer B3 count ...

  • Page 96

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.6.) Figure 1.17.17 shows the timer Bi mode ...

  • Page 97

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.17.7.) Figure 1.17.18 shows ...

  • Page 98

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table ...

  • Page 99

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timer B When measuring measurement pulse time interval from falling edge to falling edge Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing ...

  • Page 100

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Timers’ functions for three-phase motor control Use of more than one built-in timer A and timer B provides the means ...

  • Page 101

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Three-phase output buffer register Nothing is assigned attempt to ...

  • Page 102

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Timer Ai register (Note) (b15) (b8 Timer Ai-1 register (Note) (b15) (b8 Trigger select ...

  • Page 103

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Three-phase motor driving waveform output mode (three-phase waveform mode) Setting “1” in the mode select bit (bit 2 at 0348 ...

  • Page 104

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Figure 1.18.5 shows the block diagram for three-phase waveform mode. In three-phase waveform mode, the positive-phase waveforms (U phase, V ...

  • Page 105

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Figure 1.18.5. Block diagram for three-phase waveform mode Mitsubishi microcomputers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 105 M16C / 62T Group ...

  • Page 106

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit ...

  • Page 107

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which ...

  • Page 108

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Assigning certain values to DU0 (bit 0 at 034A and DUB1 (bit 1 at 034B 16 output the U phase ...

  • Page 109

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit ...

  • Page 110

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 ...

  • Page 111

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timers’ functions for three-phase motor control A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurres. Rewriting the value of timer A4. ...

  • Page 112

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O Serial I/O Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 ...

  • Page 113

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O (UART0) RxD 0 Clock source selection f 1 Internal External Clock synchronous type (when internal clock is selected) CLK polarity ...

  • Page 114

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O 1SP SP SP PAR RxDi 2SP 0 0 2SP SP SP PAR 1SP Figure 1.19.2. Block diagram of UARTi ( transmit/receive ...

  • Page 115

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O No reverse RxD data RxD2 reverse circuit Reverse 1SP SP SP PAR 2SP 0 0 2SP SP SP PAR 1SP Note 1: In M30623(80-pin ...

  • Page 116

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O UARTi transmit buffer register (b15) (b8 UARTi receive buffer register (b15) (b8 UARTi bit rate generator b7 b0 ...

  • Page 117

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O UARTi transmit/receive mode register Bit symbol SMD0 Serial I/O mode select bit SMD1 SMD2 CKDIR STPS ...

  • Page 118

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O UARTi transmit/receive control register Note 1: Set the corresponding port direction register to “0”. Note ...

  • Page 119

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O UARTi transmit/receive control register Bit symbol Nothing is assigned ...

  • Page 120

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Serial I/O UART transmit/receive control register Bit symbol U0IRS U1IRS U0RRM U1RRM CLKMD0 CLKMD1 RCSP Nothing is ...

  • Page 121

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. ...

  • Page 122

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode Table 1.19.4. Specifications of clock synchronous serial I/O mode (2) Item Select function • CLK polarity selection • LSB first/MSB first ...

  • Page 123

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode UARTi transmit/receive mode registers UART2 transmit/receive mode register b7 ...

  • Page 124

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode Table 1.19.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions ...

  • Page 125

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode • Example of transmit timing (when internal clock is selected) Transfer clock “1” Transmit enable “0” bit (TE) “1” Transmit buffer ...

  • Page 126

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode (a) Polarity select function As shown in Figure 1.19.11, the CLK polarity select bit (bit 6 at addresses 03A4 allows selection ...

  • Page 127

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock synchronous serial I/O mode (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing ...

  • Page 128

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer ...

  • Page 129

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode Table 1.19.6. Specifications of UART Mode (2) Item Select function • Separate CTS/RTS pins (UART0) • Sleep mode selection (UART0, ...

  • Page 130

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode UARTi transmit / receive mode registers UART2 transmit / receive mode register ...

  • Page 131

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode Table 1.19.7 lists the functions of the input/output pins during UART mode. This table shows the pin functions when the ...

  • Page 132

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Transfer clock “1” ...

  • Page 133

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source ...

  • Page 134

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode (c) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D transmission ...

  • Page 135

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with ...

  • Page 136

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode Transfer clock “1” Transmit enable bit(TE) “0” “1” Transmit buffer empty flag(TI) “0” Start bit TxD 2 ST RxD 2 ...

  • Page 137

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D ...

  • Page 138

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Clock asynchronous serial I/O (UART) mode Figure 1.19.24 shows the example of connecting the SIM interface. Connect T pull-up. Figure 1.19.24. Connecting the SIM interface Microcomputer ...

  • Page 139

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. UART2 Special Mode Register UART2 Special Mode Register The UART2 special mode register (address 0377 Figure 1.19.25 shows the UART2 special mode register. UART2 special mode ...

  • Page 140

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. UART2 Special Mode Register In the first place, the control bits related to the IIC bus(simplified IIC bus) interface are explained. Bit 0 of the UART ...

  • Page 141

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. UART2 Special Mode Register The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the ...

  • Page 142

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. UART2 Special Mode Register Some other functions added are explained here. Figure 1.19.27 shows their workings. Bit 4 of the UART2 special mode register is used ...

  • Page 143

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. S I/O3, 4 UART2 Special Mode Register S I/O3 I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. In M30623(80-pin package), S Figure 1.19.28 ...

  • Page 144

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. S I/O3, 4 UART2 Special Mode Register Table 1.19.10. Specifications of S I/O3, 4 Item Transfer data format • Transfer data length: 8 bits Transfer clock ...

  • Page 145

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. S I/O3, 4 UART2 Special Mode Register Functions for setting carrying out transmission, the output level of the SOUTi terminal ...

  • Page 146

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 to P10 , ...

  • Page 147

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter REF VCUT = VCUT = 1 Addresses (03C1 , 03C0 16 (03C3 , 03C2 16 (03C5 , 03C4 ...

  • Page 148

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter ...

  • Page 149

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter A-D control register 2 (Note A-D register i (b15) (b8) b7 Figure 1.20.3. A-D converter-related ...

  • Page 150

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- sion. Table ...

  • Page 151

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.20.3 ...

  • Page 152

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. ...

  • Page 153

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat ...

  • Page 154

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins ...

  • Page 155

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4 sample and hold ...

  • Page 156

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. A-D Converter Port P10 group AN 3 Analog input pins ...

  • Page 157

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. D-A Converter D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed ...

  • Page 158

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. D-A Converter D-A control register Bit symbol DA0E DA1E Nothing is assigned attempt to write to ...

  • Page 159

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. CRC CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom- puter uses a generator polynomial of CRC_CCITT ...

  • Page 160

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. CRC b15 (1) Setting 0000 16 (2) Setting 01 16 b15 The code resulting from sending ...

  • Page 161

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Programmable I/O Ports M30622(100-pin package) has 87 programmable I/O ports P10 (excluding P8 package) has 70 (P1 ...

  • Page 162

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port inside dotted-line included inside dotted-line P4 ...

  • Page 163

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Data bus Input to respective peripheral functions Data bus Input to respective peripheral ...

  • Page 164

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port P8 5 Data bus Data bus Input to respective peripheral functions P9 (inside dotted-line included (inside ...

  • Page 165

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port RESET RESET signal input BYTE Mask ROM version(inside dotted-line not included) Onetime PROM version(inside dotted-line included) BYTE signal input CNV SS CNV SS ...

  • Page 166

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Port Pi direction register (Note PDi ( 10, except 8) Bit ...

  • Page 167

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Port Pi register 10, except 8) Bit symbol Pi_0 Pi_1 ...

  • Page 168

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Pull-up control register Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Note ...

  • Page 169

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Port control register PCR0 Figure 1.23.8. Port control register Symbpl Address PCR 03FF 16 Bit ...

  • Page 170

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Programmable I/O Port Table 1.23.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding P8 ) (Note ...

  • Page 171

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Usage precaution Usage Precaution Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the ...

  • Page 172

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Usage precaution Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer ...

  • Page 173

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Usage precaution (4) External interrupt • When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". ...

  • Page 174

    ... Be especially careful during power-on. (2) One Time PROM version One Time PROM versions shipped in blank (M30622ECTFP/ECVFP, M30623ECTGP/ECVGP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following pro- cesses ...

  • Page 175

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification ...

  • Page 176

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics Table 1.26.1. Absolute maximum ratings Symbol Parameter Supply voltage Vcc AVcc Analog supply voltage RESET, V Input voltage ...

  • Page 177

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics Table 1.26.3. Electrical characteristics (referenced 16MH IN Z Parameter Symbol HIGH output ...

  • Page 178

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics Table 1.26.4. A-D conversion characteristics (referenced 16MH IN Z Symbol Parameter Resolution Absolute accuracy(8bit) Sample & hold function not ...

  • Page 179

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics Timing requirements Referenced 5V (125 C guaranteed version) unless otherwise specified. Table 1.26.6. External clock input Symbol ...

  • Page 180

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics Timing requirements Referenced 5V 125 C(125 C guaranteed version) unless otherwise specified. Table 1.26.13. Timer B ...

  • Page 181

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Timing Electrical characteristics Figure 1.26.1. Port P0 to P10 measurement circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 30pF ...

  • Page 182

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Electrical characteristics INTi input TAi input IN TAi input OUT TAi input OUT (Up/down input) During event counter mode TAi input IN (When count on falling ...

  • Page 183

    Tentative Specifications REV.A S pecifications in this manual are tentative and subject to change. Differences between M16C/62T group and M16C/61T group Group Memory space (Note 1) Memory expansion is possible 1.2M bytes mode 4M bytes mode Timer B 6 channels ...

  • Page 184

    MITSUBISHI SEMICONDUCTORS M16C/62T Group Tentative Specification REV.A Jan First Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission ...