M30622ECTFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622ECTFP Datasheet - Page 127

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M30622ECTFP

Manufacturer Part Number
M30622ECTFP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
Clock synchronous serial I/O mode
Figure 1.19.13. The transfer clock output from the multiple pins function usage
Figure 1.19.14. Serial data logic switch timing
(c) Transfer clock output from multiple pins function (UART1)
(d) Continuous receive mode
(e) Separate CTS/RTS pins function (UART0)
(f) Serial data logic switch function (UART2)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
this function is selected, UART1 CTS/RTS function cannot be used.
If the continuous receive mode enable bit (bits 2 and 3 at address 03B0
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method
of setting and the input/output pin functions are both the same, so refer to select function in the next
section, “(2) Clock asynchronous serial I/O (UART) mode.” Note that this function is invalid if the
transfer clock output from the multiple pins function is selected.
When the data logic select bit (bit6 at address 037D
reading from receive buffer register, data is reversed. Figure 1.19.14 shows the example of serial data
logic switch timing.
Tentative Specifications REV.A
S
pecifications in this manual are tentative and subject to change.
•When LSB first
Transfer clock
_______ _______
(no reverse)
Note: This applies when the internal clock is selected and transmission
(reverse)
Microcomputer
TxD
TxD
is performed only in clock synchronous serial I/O mode.
CLKS
2
2
CLK
T
X
“H”
“H”
“H”
D
“L”
“L”
“L”
1
1
1
(P6
(P6
(P6
7
4
5
)
)
)
D0
D0
_______ _______
D1
D1
D2
D2
IN
CLK
127
D3
D3
16
D4
D4
) = “1”, and writing to transmit buffer register or
D5
D5
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D6
D6
IN
CLK
D7
D7
16
, bit 5 at address 037D
16
Mitsubishi microcomputers
). (See Figure 1.19.3.)
M16C / 62T Group
16
) is

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