M30622ECTFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622ECTFP Datasheet - Page 173
M30622ECTFP
Manufacturer Part Number
M30622ECTFP
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet
1.M30622ECTFP.pdf
(184 pages)
- Current page: 173 of 184
- Download datasheet (2Mb)
Usage precaution
(4) External interrupt
(5) Rewrite the interrupt control register
Tentative Specifications REV.A
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled,
S
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set
Note 1:
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt
the interrupt request bit is not set sometimes even if the interrupt request for that register has
been generated. This will depend on the instruction. If this creates problems, use the below in-
structions to change the register.
Instructions : AND, OR, BCLR, BSET
to "1". After changing the polarity, set the interrupt request bit to "0".
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
pecifications in this manual are tentative and subject to change.
Example 1:
Example 2:
Example 3:
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
In M30623 (80-pin package), can not use INT
P1
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
5
/D
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
13
/INT
_______
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
I
I
#00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
FLG
3
to P1
_______
7
/D
15
/INT
; Disable interrupts.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
; Disable interrupts.
; Dummy read.
; Enable interrupts.
; Push Flag register onto stack
; Disable interrupts.
; Enable interrupts.
_______
_______
5
have no corresponding external pin.
173
_______
3
to INT
_______
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5
as the interrupt factors, because
Mitsubishi microcomputers
M16C / 62T Group
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