M30622ECTFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622ECTFP Datasheet - Page 38

• Manufacturer Part Number: M30622ECTFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Bus Control
Note: When using the RDY signal, always set to “0”.
Table 1.12.7. Software waits and bus cycles
ROM/RAM
(9) Software wait
External
memory
Internal
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
0005
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register's
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.12.7 shows the software wait and bus cycles. Figure 1.12.5 shows example bus timing when
using software waits.
Note 1: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
Note 2: In M30623(80-pin package), the chip select signals have no corresponding external pin.
Area
SFR
area
16
) (Note) and bits 4 to 7 of the chip select control register (address 0008
register (address 000A
Multiplex bus
Multiplex bus
Separate bus
Separate bus
Separate bus
Bus status
_______
16
) to “1”.
Wait bit
_______
Invalid
0
1
0
0
1
0
1
Bits 4 to 7 of chip select
38
control register
0 (Note)
0 (Note)
Invalid
Invalid
Invalid
0
1
0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
16
).
Mitsubishi microcomputers
Bus cycle
M16C / 62T Group