M30622ECTFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622ECTFP Datasheet - Page 42

• Manufacturer Part Number: M30622ECTFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
(2) Sub clock
(3) BCLK
(4) Peripheral function clock
(5) f
(6) f
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the X
can be reduced using the X
capacity of the X
and after a reset.
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 0006
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the X
can be reduced using the X
drive capacity of the X
stop mode and at a reset.
The BCLK is the clock that drives the CPU, and is either the main clock or fc or is derived by dividing the
main clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 0006
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
This clock has the same frequency as the main clock and is used for A-D conversion.
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
This clock has the same frequency as the sub clock. It is used for the BCLK and for the watchdog timer.
• f
• f
C32
C
1
AD
Tentative Specifications REV.A
, f
S
8
, f
pecifications in this manual are tentative and subject to change.
32,
f
1SIO2,
OUT
f
8SIO2,
pin reduces the power dissipation. This bit defaults to “1” when shifting to stop mode
COUT
f
32SIO2
16
IN
CIN
pin reduces the power dissipation. This bit changes to “1” when shifting to
-X
) to “1” and then executing a WAIT instruction.
-X
OUT
COUT
drive capacity select bit (bit 5 at address 0007
drive capacity select bit (bit 3 at address 0006
42
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
) is set to “1”.
16
Mitsubishi microcomputers
), the sub clock can be
16
16
). Reducing the drive
). However, be sure
M16C / 62T Group
16
16
). Reducing the
). Stopping the
COUT
OUT
pin
pin