M30622M4 MITSUBISHI [Mitsubishi Electric Semiconductor], M30622M4 Datasheet - Page 255

• Manufacturer Part Number: M30622M4
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Appendix Standard Serial I/O Mode (Flash Memory Version)
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
peripheral unit.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with an “H” level signal at the P5
the P5
“L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures 1.31.1 and 1.31.2 show the pin connections for the standard serial I/O mode. Serial data I/O uses
four UART1 pins: CLK
The CLK
the CMOS signal. The RTS1 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure 1.31.1 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the peripheral unit (programmer)
is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (peripheral unit, etc.) using a 4-wire clock synchronized serial I/
O (UART1). In reception, the software commands, addresses and program data are synchronized with
the rise of the transfer clock input to the CLK
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD
The TxD
When busy, either during transmission or reception, or while executing an erase operation or program,
the RTS1 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS1 (BUSY)
pin is “L” level.
Also, data in memory and the status register can be read after inputting a software command. It is pos-
sible to check flash memory operating status or whether a program or erase operation ended success-
fully or in error by reading the status register.
Software commands and the status register are explained here following.
5
(EPM) pin and an “H” level at the CNVss pin. (For the normal microprocessor mode, set CNVss to
________
1
pin is the transfer clock input pin and it inputs the external transfer clock. The TxD
1
pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
1
, RxD
1
pin.
1
, TxD
1
and RTS
1
1
(BUSY).
pin and input into the flash memory via the RxD
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0
(CE) pin, an “L” signal at
_____
Mitsubishi microcomputers
M16C / 62 Group
1
pin outputs
1
pin.
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