M30622MA-XXXFP RENESAS [Renesas Technology Corp], M30622MA-XXXFP Datasheet - Page 157

• Manufacturer Part Number: M30622MA-XXXFP
• Description: 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
• Manufacturer: RENESAS [Renesas Technology Corp]

UART2 Special Mode Register
142
Figure 1.19.27. Functional block diagram for I
P7
In the first place, the control bits related to the I
Bit 0 of the UART special mode register (0377
Setting “1” in the I
interface effective.
Table 1.19.9 shows the relation between the I
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
P7
P7
Figure 1.19.27 shows the functional block diagram for I
(IICM) causes ports P7
output terminal SCL, and port P7
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P7
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P7
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P7
refers to the interrupt that occurs when the rising edge of the SDA terminal (P7
terminal (P7
start condition detection, and set to “0” by the stop condition detection.
P7
0
1
2
/TxD
/RxD
/CLK
0
through P7
2
2
/SDA
2
/SCL
1
0
) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
) is detected with the SCL terminal (P7
Noize
Filter
Noize
Filter
Noize
2
Filter
conforming to the simplified I C bus
Selector
2
C mode select bit (bit 0) goes the circuit to achieve the I
Selector
Selector
Falling edge
detection
Timer
0
UART2
, P7
Stop condition detection
Start condition detection
IICM=1
IICM=0
1
UART2
IICM=1
I/O
Timer
I/O
IICM=0
, and P7
UART2
D
T
(Port P7
Timer
I/O
Q
L-synchronous
output enabling bit
Q
Arbitration
2
R
IICM=1
IICM=0
respectively. A delay circuit is added to the SDA transmission output,
1
External clock
output data latch)
Internal clock
IICM=1
IICM=0
2
Data bus
to work as data transmission-reception terminal SDA, clock input-
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
Port reading
delay
2
2
16
2
C mode select bit and respective control workings.
UART2
2
CLK
S
C mode
R Q
C bus (simplified I
) is used as the I
Transmission
register
Reception register
Bus busy
1
UART2
UART2
) staying “H”. The stop condition detection interrupt
Bus collision
detection
9th pulse
2
D
D
C mode. Setting “1” in the I
T
T
Q
Q
1
of the direction register.
ACK
0
. The interrupt factors of the bus collision
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
2
NACK
C mode selection bit.
2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
C bus) interface are explained.
IICM=0
UART2 reception/ACK
interrupt request
DMA1 request
Bus collision/start, stop
condition detection
interrupt request
UART2 transmission/
NACK interrupt
request
2
C bus (simplified I
0
) is detected with the SCL
2
C mode selection bit
Mitsubishi microcomputers
1
M16C / 62 Group
(SCL) results in
To DMA0, DMA1
To DMA0
2
C bus)