M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 12

• Manufacturer Part Number: M30622SAFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

CPU
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(3) Frame base register (FB)
(4) Program counter (PC)
(5) Interrupt table register (INTB)
(6) Stack pointer (USP/ISP)
(7) Static base register (SB)
(8) Flag register (FLG)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
• Bit 0: Carry flag (C flag)
• Bit 1: Debug flag (D flag)
• Bit 2: Zero flag (Z flag)
• Bit 3: Sign flag (S flag)
• Bit 4: Register bank select flag (B flag)
• Bit 5: Overflow flag (O flag)
• Bit 6: Interrupt enable flag (I flag)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M16C / 62A Group
Mitsubishi microcomputers