M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 136

• Manufacturer Part Number: M30622SAFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

UART2 Special Mode Register
136
Figure 1.16.27. Functional block diagram for I
Table 1.16.9. Features in I
10
11
1
2
3
4
5
6
7
8
9
P7
P7
P7
Note 1: Make the settings given below when I
Note 2: Follow the steps given below to switch from a factor to another.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
P7
Factor of interrupt number 10 (Note 2)
Factor of interrupt number 15 (Note 2)
Factor of interrupt number 16 (Note 2)
UART2 transmission output delay
P7
P7
P7
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits
Noise filter width
Reading P7
Initial value of UART2 output
0
2
1
/TxD
/CLK
/RxD
2
0
1
0
2
at the time when UART2 is in use
2
at the time when UART2 is in use
at the time when UART2 is in use
through P7
2
/SDA
/SCL
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
1
Function
Filter
Filter
Noize
Noize
2
Noize
Filter
Selector
conforming to the simplified I C bus
Digital delay
(Divider)
Timer
Selector
Selector
UART2
Falling edge
detection
Timer
I/O
IICM=0
IICM=1
SDDS=1 and
DL 000
SDDS=0
or DL=000
IICM=1
UART2
IICM=0
UART2
2
D
(Port P7
T
I/O
C mode
Q
Start condition
detection
Stop condition
detection
Timer
I/O
Q
IICM=1
IICM=0
1
R
output data latch)
L-synchronous
output enabling
bit
2
External clock
C mode is in use.
Internal clock
Data bus
Port reading
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
SDHI
SWC2
IICM=1 (SDDS=0) or
DL=000 (SDDS=1)
IICM=0 or
DL 000 (SDDS=1)
2
Bus collision detection
UART2 transmission
UART2 reception
Not delayed
TxD
RxD
CLK
UART2 reception
15ns
Reading the terminal when 0 is
assigned to the direction register
H level (when 0 is assigned to
the CLK polarity select bit)
S
R
Analog
Q
delay
Arbitration
2
CLK
control
2
2
Reception register
ALS
(output)
(input)
Bus busy
UART2
Falling edge of 9 bit
2
UART2
Bus collision
detection
C mode
Normal mode
9th pulse
Transmission
register
SWC
D
D
UART2
T
T
Q
Q
1
of the direction register.
ACK
IICM=1
IICM=0
NACK
IICM=1
and IICM2=0
IICM=0
or IICM2=1
IICM=1
and IICM2=0
IICM=0
or IICM2=1
Bus collision/start, stop condition
detection interrupt request
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 reception/ACK interrupt
request, DMA1 request
UART2 transmission/
NACK interrupt request
Start condition detection or stop
condition detection
SDA (input/output) (Note 3)
Acknowledgment detection (ACK)
50ns
Reading the terminal regardless of the
value of the direction register
The value set in latch P7
selected
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed
SCL (input/output)
P7
2
I
2
C mode (Note 1)
M16C / 62A Group
Mitsubishi microcomputers
0
To DMA0
To DMA0, DMA1
when the port is