M30622SAFP MITSUBISHI [Mitsubishi Electric Semiconductor], M30622SAFP Datasheet - Page 240

• Manufacturer Part Number: M30622SAFP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
_____
________
leased, which is done when the P5
(CE) pin is "H" level, the P5
(EPM) pin "L" level and the CNVss pin "H"
0
5
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 1.29.1 and 1.29.2 show the pin connections for the standard
serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/
O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level
of CLK
pin when the reset is released.
1
To use standard serial I/O mode 1 (clock synchronized), set the CLK
pin to "H" level and release the reset.
1
The operation uses the four UART1 pins CLK
, RxD
, TxD
and RTS
(BUSY). The CLK
pin is the transfer
1
1
1
1
1
clock input pin through which an external transfer clock is input. The TxD
pin is for CMOS output. The
1
RTS
(BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.
1
To use standard serial I/O mode 2 (clock asynchronized), set the CLK
pin to "L" level and release the
1
reset. The operation uses the two UART1 pins RxD
and TxD
.
1
1
In the standard serial I/O mode, only the user ROM area indicated in Figure 1.29.19 can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit are not accepted unless the ID code matches.
240