TS8388BCF ATMEL [ATMEL Corporation], TS8388BCF Datasheet
TS8388BCF
Related parts for TS8388BCF
TS8388BCF Summary of contents
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Features • 8-bit Resolution • ADC Gain Adjust • 1.5 GHz Full Power Input Bandwidth (-3 dB) • 1 GSPS (min) Sampling Rate • SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc GSPS, ...
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Functional Description Block Diagram The following figure shows the simplified block diagram. Figure 1. Simplified Block Diagram MASTER/SLAVE TRACK & HOLD AMPLIFIER INB G=2 T/H G=1 CLK, CLKB CLOCK BUFFER DRRB DR, DRB Functional The TS8388B ...
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Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltage Analog input voltages Maximum difference between V and V IN ...
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Table 2. Recommended Operating Conditions (Continued) Parameter Symbol Differential analog input voltage V (Full Scale) V Clock input power level P Operating temperature range T Electrical Operating Digital outputs Characteristics Tj (typical) = ...
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Table 3. Electrical Specifications (Continued) Parameter Positive supply current Negative supply voltage Negative supply current Nominal power dissipation Power supply rejection ratio Resolution Analog Inputs Full Scale Input Voltage range (differential mode) (0V common mode voltage) Full Scale Input Voltage ...
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Table 3. Electrical Specifications (Continued) Parameter Digital Outputs Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format, Tj (typical Logic compatibility for digital outputs (Depending on the value ...
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Table 3. Electrical Specifications (Continued) Parameter Gain error drift Offset error drift DC Accuracy (CQFP68 package) Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format Tj (typical Differential non linearity Differential ...
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Table 3. Electrical Specifications (Continued) Parameter Effective Number Of Bits GSPS MHz GSPS 500 MHz GSPS 1000 MHz (-1 dBFs) ...
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Table 3. Electrical Specifications (Continued) Parameter Data ready output delay Data ready reset delay Data to data ready – Clock low pulse width (See “Timing Diagrams” on page 10.) Data to data ready output delay (50% duty cycle ...
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Timing Diagrams Figure 2. TS8388B Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level (VIN, VINB) X N-1 (CLK, CLKB) 1360 ps DIGITAL 1000 ps OUTPUTS TDR = 1320 ps Data Ready (DR, DRB) DRRB ...
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Explanation of Test Levels Table 4. Explanation of Test Levels Num Notes: Functions Description Table 5. Functions Description Name Function V Positive power supply CC V Analog negative power supply EE V Digital positive power supply PLUSD GND Ground V ...
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Digital Output NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt- age errors. Coding Table 6. Digital Output Coding Differential Analog Input Voltage Level > +251 mV > Positive full scale + 1/2 ...
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Package Description Pin Description Table 7. TS8388BGL Pin Description (CBGA68 package) Symbol Pin number GND A2, A5, B1, B5, B10, C2, D2, E1, E2, E11, F1, F2, G11, K2, K3, K4, K5, K10, L2 A4, A6, B2, B4, ...
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TS8388BGL Pinout Figure 4. TS8388BGL Pinout of CBGA 68 Package Gorb 6 VCC 5 GND 4 VCC 3 VEE 2 GND 1 NC Ball A1 Index A other side TS8388B 14 ...
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Table 8. TS8388BF/TS8388BFS Pin Description (CQFP68 package) Symbol Pin number GND 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58 16, 17, 18, 68 PLUSD V 26, 29, 32, 33, ...
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TS8388BF/ TS8388BFS Pinout Figure 5. TS8388BF/TS8388BFS Pinout of CQFP68 package VPLUSD D2B D1B D0B 25 GORB VCC 26 27 GND 28 GND ...
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Typical Characterization Results Static Linearity MSPS/F S Figure 6. Integral Non Linearity Note: Figure 7. Differential Non Linearity Note: 2144C–BDC–04/ MHz IN Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz; Positive peak: 0.78 ...
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Effective Number Figure 8. Effective Number of Bits = Bits Versus Power Supplies Variation Figure 9. Effective Number of Bits = f (V Figure 10. Effective Number of Bits = f (V TS8388B 18 EEA 8 7 ...
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Typical FFT Results Figure 11 GSPS MHz S IN Figure 12 GSPS 495 MHz S IN Figure 13 GSPS 995 MHz (-3 dB Full ...
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Spurious Free Dynamic Range Versus Input Amplitude Figure 14. Sampling Frequency: F SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding Figure 15. Sampling Frequency: F SINAD = ...
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Dynamic GSPS Performance Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and Versus Analog clock inputs. Input Frequency Figure 16. ENOB (dB 200 Figure ...
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Effective Number Analog Input Frequency Bits (ENOB) Clock duty cycle 50/50, Binary output coding Versus Sampling Frequency Figure 19. ENOB (dB) 8 FIN = FS/2 7 FIN = 500 MHz 200 SFDR ...
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TS8388B ADC Performances Versus Junction Temperature Figure 21. Effective Number of Bits Versus Junction Temperature GSPS 500 MHz; Duty Cycle = 50 -40 -20 Figure 22. Signal ...
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Figure 24. Power Consumption Versus Junction Temperature GSPS 500 MHz; Duty Cycle = 50 -40 -20 Typical Full Power Input Bandwidth Figure 25. 1.8 GHz at -3 ...
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Figure 26. 1.5 GHz (-2 dBm Full Power Input) – CQFP68 package 100 300 2144C–BDC–04/03 Frequency (MHz) 500 700 900 1100 TS8388B 1300 1500 1700 25 ...
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ADC Step Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps. Response Note: Figure 27. Test Pulse Digitized with 20 GHz DSO 0 0.5 1.0 Figure 28. Same Test Pulse Digitized with TS8388B ...
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TS8388B Main Features Timing Information Timing Value for Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simula- TS8388B tions and first characterizations results fitted with measurements. Timing values are given at package ...
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Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other terms : – – The external (on board) skew effect has NOT been ...
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Data Ready Output The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels Signal Restart (-0.8V). DRRB may also be Grounded allowed to float, for normal free running Data Ready output signal. The ...
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Differential Versus The TS8388B can operate at full speed in either differential or single-ended configuration. Single-ended Analog This is explained by the fact the ADC uses a high input impedance differential preamplifier Input Operation stage, (preceeding the Sample and hold ...
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No performance degradation (i.e.: due to timing jitter) is observed in this particular single- ended configuration up to 1.2 GSPS Nyquist conditions (F This is true so long as the inverted phase clock input pin the neighboring ...
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Single-ended ECL In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock Clock Input input pin CLKB (respectively CLK) connected to -1.3V through the 50 termination resistor. The inphase input amplitude is 1V peak to peak, ...
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Three possible line driving and back-termination scenarios are proposed (assuming V 0V Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading Each output voltage varies between -1.02V and -1.35V (respectively ...
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Differential Output Loading Configurations (Levels for ECL Compatibility) Figure 34. Differential Output: 75 VPLUSD = 0V -0.8V 75Ω 75Ω DVEE Figure 35. Differential Output: 50 VPLUSD = 0V -0.8V 75Ω 75Ω DVEE ...
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Figure 36. Differential Output: Open Loaded VPLUSD = 0V -0.8V 75Ω 75Ω DVEE Differential Output Loading Configurations (Levels for LVDS Compatibility) Figure 37. Differential Output: 75 VPLUSD = 2.4V 1.6V 75Ω 75Ω ...
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Figure 38. Differential Output: 50 VPLUSD = 2.4V 1.6V 75Ω 75Ω DVEE Figure 39. Differential Output: Open Loaded VPLUSD = 2.4V 1.6V 75Ω 75Ω DVEE Out of Range Bit An Out of ...
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A standard technique for reducing the amplitude of such errors down to putting the digital datas in Gray code format. Though the TS8388B has been designed for featuring a Bit Error Rate of 10 select between the Binary or Gray ...
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Figure 41. ADC Gain Control Pin 60 Note: TS8388B 38 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 -500 -400 -300 -200 -100 Vgain (command voltage) (mV) For more information, please refer to the document "DEMUX and ADCs Application ...
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Equivalent Input/Output Schematics Figure 42. Equivalent Analog Input Circuit and ESD Protections VCC = +5V -0.8V GND = 0V -5.8V 50Ω E21V VEE VIN Pad capacitance 340 fF 5.8V 0.8V E21G Note: The ESD protection equivalent capacitance is 150 fF. ...
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Figure 44. Equivalent Data Output Buffer Circuit and ESD Protections E01V VEE OUT Pad capacitance 180 fF E21GA VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. Figure 45. ADC Gain Adjust Equivalent Analog Input Circuit and ...
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Figure 46. GORB Equivalent Input Schematic and ESD Protections GORB: Gray or Binary Select Input; Floating or Tied to VCC -> Binary VEE GORB Pad capacitance 180 fF VEE = -5V Note: The ESD protection equivalent capacitance is 150 fF. ...
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TSEV8388B: For complete specification, see separate TSEV8388B document. Device Evaluation Board General The TSEV8388B Evaluation Board (EB board which has been designed in order to facili- tate the evaluation and the characterization of the TS8388B device up to ...
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CBGA68 Thermal and Moisture Characteristics Thermal Resistance The following table lists the converter thermal performance parameters of the device itself, from Junction to with no external heatsink added. Ambient: RTHJA Table 9. Thermal Resitance Figure 48. Thermal Resistance from Junction ...
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CBGA68 Board It is recommended to use an external heatsink or PCBoard special design. Assembly with Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated External Heasink in the device. Figure 49. CBGA68 Board Assembly Moisture This ...
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Nominal CQFP68 Although the power dissipation is low for this performance, the use of a heat sink is mandatory. Thermal Characteristics The user will find some advice on this topics below. Thermal Resistance The following table lists the converter thermal ...
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Thermal Resistance Typical value for Rthjc is given to 4.75 C/W. from Junction to Case: RTHJC CQFP68 Board Assembly Figure 51. CQFP68 Board Assembly with External Heatsink Printed circuit Aluminum heatsink Interface: Af-filled ...
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Enhanced CQFP68 Thermal Characteristics Enhanced CQFP68 The CQFP68 has been modified, in order to improve the thermal characteristics: • A CuW heatspreader has been added at the bottom of the package. • The die has been electrically isolated with the ...
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Definitions Definition of Terms (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that dif- fers by more than (FPBW) Full Power Analog input frequency at which the fundamental ...
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Aperture Sample to sample variation in aperture delay. The voltage error due to jitter depends on the Uncertainty slew rate of the signal at the sampling point. (TS) Settling Time Time delay to achieve 0.2% accuracy at the converter ...
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... Table 11. Ordering Information Part Number Package JTS8388B-1V1B Die JTS8388B-1V2B Die TS8388BCF CQFP 68 TS8388BVF CQFP 68 TS8388BMF CQFP 68 TS8388BMF B/Q CQFP 68 TS8388BMF B/T CQFP 68 TS8388BCFS CQFP 68 with heatspreader TS8388BVFS CQFP 68 with heatspreader TS8388BMFS CQFP 68 with heatspreader TS8388BMFS B/Q CQFP 68 with heatspreader TS8388BMFS B/T CQFP 68 with heatspreader TS8388BMFS9NB2 CQFP 68 with ...
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Table 11. Ordering Information Part Number Package TS8388BCGL CBGA 68 TS8388BVGL CBGA 68 TSEV8388BF CQFP 68 TSEV8388BFZA2 CQFP 68 TSEV8388BGL CBGA 68 TSEV8388BGLZA2 CBGA 68 2144C–BDC–04/03 Temperature Range Screening "C" grade Standard 0 C < Tc; Tj < ...
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CBGA68 Capacitors and Resistors Implant Figure 53. TS8388BGL Capacitors and Resistors Implant ∅ 7.0 mm 0.9 mm Only on-package marking Electrically isolated Note: TS8388B 52 0.9 mm GND 100 pF DVEE VEE VCC VEE CLKB 100 pF 100 pF 100 ...
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Outline Descriptions Figure 54. Package Dimension – 68 Pins CBGA CBGA 68 package. AL203 substrate. Package design. Corner balls (x4) are not connected (mechanical ball). Balls : 1.27 mm pitch on 11x11 grid. View balls side 1. ...
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Outline Figure 55. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP) Dimensions TS8388B 54 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N° 1 index 1.27 BSC CQFP 68 0.950 ± 0.006 24.13 ± 0.152 1.133 - 1.147 ...
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Figure 56. Package Dimension – 68-lead Enhanced CQFP with Heatspreder 2144C–BDC–04/03 TOP VIEW 0.8 BCS 20.32 BSC 0.050 BCS Pin N° 1 index 1.27 BSC CQFP 68 0.950 ± 0.006 24.13 ± 0.152 1.133 - 1.147 28.78 - 29.13 0.027 ...
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Datasheet Status Description Table 12. Datasheet Status Datasheet Status Objective specification Target specification Preliminary specification -site Preliminary specification -site Product specification Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...