AK5700VN AKM [Asahi Kasei Microsystems], AK5700VN Datasheet

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AK5700VN

Manufacturer Part Number
AK5700VN
Description
16-Bit ?? Mono ADC with PLL & MIC-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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ASAHI KASEI
The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto
Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports
base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a
24pin QFN, utilizing less board space than competitive offerings.
MS0569-E-01
1. Resolution: 16bits
2. Recording Function
3. Sampling Rate:
4. PLL Input Clock:
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
7. μP I/F: 3-wire Serial
8. Power Supply:
9. Power Supply Current: 6mA
10. Ta = −30 ∼ 85°C
11. Package: 24pin QFN (4mm x 4mm)
12. Pin and Register compatible with AK5701 Stereo Version
- Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
- PLL Slave Mode (EXLRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
- PLL Master Mode:
- EXT Slave Mode:
- MCKI pin:
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
- DSP Mode, 16bit MSB justified, I
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
16-Bit ΔΣ Mono ADC with PLL & MIC-AMP
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
GENERAL DESCRIPTION
FEATURES
- 1 -
2
S
AK5700
[AK5700]
2006/12

Related parts for AK5700VN

AK5700VN Summary of contents

Page 1

ASAHI KASEI The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports base-band clock of mobile phone, therefore it ...

Page 2

ASAHI KASEI Block Diagram AIN1/AIN+ S AIN− AIN2 MPWR VCOM AVDD AVSS VCOC PLL MCKO MCKI MS0569-E-01 ALC Audio I/F or ADC HPF Controller IVOL Control Register CSP CSN CCLK CDTI Figure 1. Block Diagram - 2 - ...

Page 3

... QFN (0.5mm pitch AK5700VN 10 9 Top View 8 7 AK5701VN 2 channel 2 Stereo Input Selector DSP Mode 0, DSP Mode 1, 2 Left justified [AK5700] EXLRCK EXSDTI MCKO CSP SDTO LRCK AK5700VN 1channel 2 Mono Input Selector DSP Mode 0, 2 Left justified 2006/12 ...

Page 4

ASAHI KASEI No. Pin Name I/O Common Voltage Output Pin, 0.5 x AVDD 1 VCOM O Bias voltage of ADC inputs. 2 AVSS - Analog Ground Pin 3 AVDD - Analog Power Supply Pin 4 DVDD - Digital Power Supply ...

Page 5

ASAHI KASEI (AVSS, DVSS=0V; Note 2) Parameter Power Supplies: Analog Digital |AVSS – DVSS| (Note 3) Input Current, Any Pin Except Supplies Analog Input Voltage (Note 4) Digital Input Voltage (Note 5) Ambient Temperature (powered applied) Storage Temperature Note 2. ...

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ASAHI KASEI (Ta=25°C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter MIC Amplifier: AIN1, AIN2 pins; MDIF1 bit = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” ...

Page 7

ASAHI KASEI (Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; fs=44.1kHz) Parameter ADC Digital Filter (Decimation LPF): ±0.1dB Passband (Note 14) −1.0dB −3.0dB Stopband (Note 14) Passband Ripple Stopband Attenuation Group Delay (Note 15) Group Delay Distortion ADC Digital Filter (HPF): ...

Page 8

ASAHI KASEI (Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; C Parameter PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency Pulse Width Low Pulse Width High MCKO Output Timing Frequency Duty Cycle Except 256fs at fs=32kHz, ...

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ASAHI KASEI Parameter PLL Slave Mode (PLL Reference Clock = EXBCLK pin) EXLRCK Input Timing Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle EXBCLK Input Timing Period PLL3-0 bits = “0010” PLL3-0 bits = “0011” Pulse Width ...

Page 10

ASAHI KASEI Parameter Audio Interface Timing (DSP Mode) Master Mode LRCK “↑” to BCLK “↑” (Note 17) LRCK “↑” to BCLK “↓” (Note 18) BCLK “↑” to SDTO (BCKP bit = “0”) BCLK “↓” to SDTO (BCKP bit = “1”) ...

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ASAHI KASEI Parameter Control Interface Timing (CSP pin = “L”) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface ...

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ASAHI KASEI Timing Diagram MCKI tCLKH LRCK BCLK MCKO Figure 2. Clock Timing (PLL/EXT Master mode) LRCK BCLK (BCKP = "0") BCLK (BCKP = "1") SDTO Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”) ...

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ASAHI KASEI LRCK BCLK (BCKP = "1") BCLK (BCKP = "0") SDTO Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) LRCK tMBLR BCLK SDTO Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except ...

Page 14

ASAHI KASEI EXLRCK EXBCLK (BCKP = "0") EXBCLK (BCKP = "1") Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0) EXLRCK EXBCLK (BCKP = "1") EXBCLK (BCKP = ...

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ASAHI KASEI MCKI tCLKH EXLRCK tLRCKH EXBCLK tBCKH MCKO Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) EXLRCK EXBCLK (BCKP = "0") EXBCLK (BCKP = "1") SDTO Figure 9. Audio Interface ...

Page 16

ASAHI KASEI EXLRCK tLRB EXBCLK (BCKP = "1") EXBCLK (BCKP = "0") SDTO Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1) MCKI EXLRCK EXBCLK Figure 11. Clock Timing (EXT Slave mode) MS0569-E-01 tLRCKH tBSD 1/fCLK ...

Page 17

ASAHI KASEI EXLRCK tBLR EXBCLK tLRD SDTO Figure 12. Audio Interface Timing (PLL/EXT Slave mode) MS0569-E-01 tLRB tBSD MSB - 17 - [AK5700] VIH VIL VIH VIL 50%DVDD 2006/12 ...

Page 18

ASAHI KASEI CSN CCLK CDTI Figure 13. WRITE Command Input Timing (CSP pin = “L”) CSN CCLK CDTI D2 Figure 14. WRITE Data Input Timing (CSP pin = “L”) MS0569-E-01 tCSS tCCKL tCCKH tCCK tCDS tCDH C1 C0 tCSH D1 ...

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ASAHI KASEI CSN CCLK CDTI Figure 15. WRITE Command Input Timing (CSP pin = “H”) CSN CCLK CDTI D2 Figure 16. WRITE Data Input Timing (CSP pin = “H”) MS0569-E-01 tCSS tCCKL tCCKH tCCK tCDS tCDH C1 C0 tCSH D1 ...

Page 20

ASAHI KASEI PMADC bit SDTO PDN MS0569-E-01 tPDV Figure 17. Power Down & Reset Timing 1 tPD Figure 18. Power Down & Reset Timing [AK5700] 50%DVDD VIL 2006/12 ...

Page 21

ASAHI KASEI System Clock There are the following five clock modes to interface with external devices (see Table 1 and Table 2.) Mode PLL Master Mode (Note 22) PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode ...

Page 22

ASAHI KASEI PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the ...

Page 23

ASAHI KASEI When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits (See Table 6). FS3 bit FS2 bit Mode Don’t care ...

Page 24

ASAHI KASEI PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated ...

Page 25

ASAHI KASEI PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, EXBCLK or EXLRCK pin. The required clock to the AK5700 is generated by an ...

Page 26

ASAHI KASEI EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK5700 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is ...

Page 27

ASAHI KASEI EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”) The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the ...

Page 28

ASAHI KASEI Bypass Mode When THR bit = “1”, M/S bit = “0” and PMADC bit = “0” input clocks and data of EXLRCK, EXBCLK and EXSDTI pins are bypassed to LRCK, BCLK and SDTO pins, respectively. When THR bit ...

Page 29

ASAHI KASEI Audio Interface Format Fore types of data format are available and are selected by setting the DIF1-0 bits (see Table 15). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be ...

Page 30

ASAHI KASEI EXLRCK / LRCK (M/S=0) EXLRCK / LRCK (M/S= EXBCLK(32fs) BCLK(32fs) 8 SDTO( 15:MSB, 0:LSB Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”, M/S = “0” or ...

Page 31

ASAHI KASEI EXLRCK LRCK EXBCLK(32fs) BCLK(32fs SDTO( EXBCLK(64fs) BCLK(64fs SDTO(o) 15:MSB, 0:LSB Figure 30. Mode 2 Timing (MSB justified, ...

Page 32

ASAHI KASEI Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is selected by HPF1-0 bits (see Table 17) and scales with sampling rate (fs). The default ...

Page 33

ASAHI KASEI Figure 33. Connection Example for Full-differential Mic Input (MDIF1bit = “1”) MIC Gain Amplifier The AK5700 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 20). The typical ...

Page 34

ASAHI KASEI ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. 1. ALC Limiter Operation During the ALC limiter operation, when the output exceeds the ALC limiter detection level (Table 22), the ...

Page 35

ASAHI KASEI 2. ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits (Table 25 set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table ...

Page 36

ASAHI KASEI 3. Example of ALC Operation Table 28 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH Limiter detection Level ZELMN Limiter zero crossing detection ZTM1-0 Zero crossing timeout period Recovery waiting period WTM1-0 ...

Page 37

ASAHI KASEI Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. After exiting reset state, set-up the registers for the ALC ...

Page 38

ASAHI KASEI When writing to the IVL7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL is not changed since zero crossing counter is reset at every write operation. If ...

Page 39

ASAHI KASEI Serial Control Interface Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). CSP pin selects the polarity of CSN pin and chip address. 1) CSP pin = “L” The data on ...

Page 40

ASAHI KASEI Register Map Addr Register Name 10H Power Management 11H PLL Control 12H Signal Select 13H Mic Gain Control 14H Audio Format Select 15H fs Select HPF1 16H Clock Output Select 17H Reserved 18H Input Volume Control IVL7 19H ...

Page 41

ASAHI KASEI Register Definitions Addr Register Name D7 10H Power Management 0 Default 0 PMADC: MIC-Amp and ADC Power Management 0: Power down (Default) 1: Power up When the PMADC bit is changed from “0” to “1”, the initialization cycle ...

Page 42

ASAHI KASEI Addr Register Name 12H Signal Select Default AIN: ADC Input Source Select 0: AIN1 pin (Default) 1: AIN2 pin MDIF1: ADC Input Type Select 0: Single-ended input (AIN1/AIN2 pin: Default) 1: Full-differential input (AIN+/AIN− pin) PMMP: MPWR pin ...

Page 43

ASAHI KASEI Addr Register Name 15H fs Select HPF1 Default FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (See Table 11) Default: “1111” (44.1kHz) FS3-0 bits select sampling frequency at PLL mode and MCKI ...

Page 44

ASAHI KASEI Addr Register Name 1AH Timer Select Default WTM1-0: ALC Recovery Waiting Period (see Table 25) Default: “00” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 24) Default: “00” (128/fs) Addr Register Name 1BH ALC Mode ...

Page 45

ASAHI KASEI Addr Register Name 1DH Mode Control 1 Default TE3-0: EXT Master Mode Enable When TE3-0 bits is set to “0101”, the write operation to addr=1EH is enabled. TE3-0 bits should be set to “1010” except for EXT Master ...

Page 46

... Cp in parallel with Cp+Rp improves PLL jitter characteristics. - Mic input AC coupling capacitor should be 1μF or less to start the recording within 100ms. Figure 39. Typical Connection Diagram (MIC Input) MS0569-E-01 SYSTEM DESIGN 19 MPWR EXLRCK EXSDTI 20 TEST AK5700VN 21 AIN2 Top View 22 AIN‐ AIN1 23 VCOC 24 Rp ...

Page 47

... When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. Figure 40. Typical Connection Diagram (Line Input) MS0569-E-01 19 MPWR EXLRCK EXSDTI 20 TEST AK5700VN AIN2 21 Top View 22 AIN− AIN1 23 VCOC 24 ...

Page 48

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK5700 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence ...

Page 49

ASAHI KASEI Clock Set up When ADC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (4) MCKO bit (Addr:16H, D2) PMPLL bit (Addr:11H, D0) (5) MCKI ...

Page 50

ASAHI KASEI 2. PLL Slave Mode (EXLRCK or EXBCLK pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” ...

Page 51

ASAHI KASEI 3. PLL Slave Mode (MCKI pin) Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (4) MCKO bit (Addr:16H, D2) PMPLL bit (Addr:11H, D0) (5) MCKI pin MCKO pin EXBCLK pin EXLRCK pin <Example> (1) After ...

Page 52

ASAHI KASEI 4. EXT Slave Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) (4) MCKI pin (4) EXLRCK pin EXBCLK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is ...

Page 53

ASAHI KASEI 5. EXT Master Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) MCKI pin M/S bit (Addr:11H, D1) TE3-0 bits "1010" (Addr:1DH, D7-4) TMASTER bit (Addr:1EH, D1) BCLK pin LRCK pin <Example> (1) After Power ...

Page 54

ASAHI KASEI 6. Slave & Bypass Mode Power Supply (1) PDN pin (2) (3) PMVCM bit (Addr:10H, D2) PMPLL bit (Addr:11H, D0) EXLRCK pin EXBCLK pin Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns ...

Page 55

ASAHI KASEI 7. Bypass Mode Power Supply (1) PDN pin (2) THR bit (Addr:16H, D3) (3) EXLRCK pin EXBCLK pin EXSDTI pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset ...

Page 56

ASAHI KASEI MIC Input Recording FS3-0 bits X,XXX (Addr:15H, D3-0) (1) MIC Control 0, 01 (Addr:12H, D4 (2) & Addr:13H, D1-0) Timer Control XXH (Addr:1AH) (3) ALC Control 1 XXH (Addr:1BH) (4) ALC Control 2 XXH (Addr:1CH) (5) ALC State ...

Page 57

ASAHI KASEI Stop of Clock Master clock can be stopped when ADC is not used. 1. PLL Master Mode (1) PMPLL bit (Addr:11H, D0) M/S bit (Addr:11H, D1) (2) MCKO bit "H" or "L" (Addr:16H, D2) (3) External MCKI Input ...

Page 58

ASAHI KASEI 3. PLL Slave Mode (MCKI pin) (1) PMPLL bit (Addr:11H, D0) (2) MCKO bit (Addr:16H, D2) (3) External MCKI Input <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO output: MCKO bit = ...

Page 59

ASAHI KASEI Power down Power supply current is typ. 20μA by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be shut down (typ. 1μA) by stopping clocks and ...

Page 60

ASAHI KASEI 24pin QFN (Unit: mm) 4.0 ± 0 0.08 0.5 Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. Material & Lead finish Package molding compound: Lead ...

Page 61

ASAHI KASEI Date (YY/MM/DD) Revision Reason 06/11/16 00 First Edition 06/12/25 01 Error correct • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) ...

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