AK4344ET AKM [Asahi Kasei Microsystems], AK4344ET Datasheet

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AK4344ET

Manufacturer Part Number
AK4344ET
Description
100dB 96kHz 24-Bit Stereo 3.3V ?? DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
The AK4344 is a 24bit low voltage & low power stereo. The AK4344 uses the Advanced Multi-Bit ΔΣ
architecture, which achieves DR=100dB at 3.3V operation. The AK4344 integrates a combination of SCF
and CTF filters increasing performance for systems with excessive clock jitter. The output voltage level
can be set as high as 1Vrms. The AK4344 is offered in a space saving 16pin TSSOP package.
MS0641-E-00
Sampling Rate: 8kHz ∼ 96kHz
24-Bit 8 times FIR Digital Filter
SCF with high tolerance to clock jitter
Single-ended output buffer
Digital de-emphasis for 32kHz, 44.1kHz, 48kHz sampling
I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I
Master Clock:
µP Interface: 4-wire/3-wire
CMOS Input Level
THD+N: -90dB(0dB)
DR, S/N: 100dB
DAC output voltage level: 1Vrms (@VDD=3.3V)
Power Supply: 2.7 to 3.6V
Ta = −20 ∼ 85°C
16pin TSSOP
512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz)
256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz)
128/192/256/384fs for Double Speed (48kHz ∼ 96kHz)
100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC
GENERAL DESCRIPTION
FEATURES
- 1 -
AK4344
2
S Compatible
2007/06

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AK4344ET Summary of contents

Page 1

The AK4344 is a 24bit low voltage & low power stereo. The AK4344 uses the Advanced Multi-Bit ΔΣ architecture, which achieves DR=100dB at 3.3V operation. The AK4344 integrates a combination of SCF and CTF filters increasing performance for systems with ...

Page 2

CSN CCLK Interface CDTI CDTO SDTI1 Audio Data LRCK Interface BICK TEST1 PDN CSN CCLK Interface CDTI SDTI2 Audio SDTI1 Data LRCK Interface BICK TEST1 PDN MS0641-E-00 µP De-emphasis Control 8X Modulator Interpolator 8X Interpolator Modulator TEST2 Figure 1. AK4344 ...

Page 3

... Ordering Guide AK4344ET AKD4344 ■ Pin Layout MCLK 1 BICK 2 SDTI1 3 LRCK 4 PDN 5 CSN 6 CCLK 7 CDTI 8 MS0641-E-00 −20 ∼ +85°C 16pin TSSOP (0.65mm pitch) Evaluation Board for AK4344 AK4344 13 Top 12 View TEST2 CDTO/ SDTI2 VDD VSS VCOM LOUT ...

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No. Pin Name I/O 1 MCLK I 2 BICK I 3 SDTI1 I 4 LRCK I 5 PDN I 6 CSN I 7 CCLK I 8 CDTI I 9 TEST1 I 10 ROUT O 11 LOUT O 12 VCOM O ...

Page 5

Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Temperature (Powered applied) Storage Temperature Note 1. All voltages with respect to ground. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 ...

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VDD=3.3V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter Dynamic Characteristics (GAIN bit= “1”) : Resolution THD+N DR S/N Interchannel Isolation DC Accuracy: Interchannel ...

Page 7

VDD=2.7 ∼ 3.6V; fs=44.1kHz; DEM1 bit= “0”, DEM0 bit= “1”) Parameter DAC Digital Filter: Passband (Note 8) Stopband Passband Ripple Stopband Attenuation Group Delay Digital Filter + SCF + CTF: 0 ∼ 20kHz Frequency Response ∼ 40kHz Note 8. ...

Page 8

VDD=2.7 ∼ 3.6V 20pF) L Parameter Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) Duty Cycle LRCK Frequency Half Speed Mode (DFS1-0 = “10”) Normal Speed Mode (DFS1-0 = “00”) ...

Page 9

Timing Diagram MCLK tCLKH LRCK BICK LRCK tBLR BICK SDTI MS0641-E-00 1/fCLK tCLKL 1/fs tBCK tBCKH tBCKL Figure 3. Clock Timing tLRB tSDS Figure 4. Serial Interface Timing - 9 - dCLK=tCLKH x fCLK, tCLKL x fCLK tSDH VIH ...

Page 10

CSN CCLK CDTI CDTO Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode CSN CCLK CDTI D3 CDTO Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode CSN CCLK CDTI A1 CDTO Figure 7. READ Data Output Timing ...

Page 11

CSN CCLK CDTI CDTO D3 Figure 8. READ Data Output Timing 2 in 4-wire serial mode PDN MS0641-E- tPD Figure 9. Power-Down & Reset Timing - 11 - tCSW VIH VIL tCSH VIH VIL VIH VIL tCCZ Hi-Z ...

Page 12

System Clock The external clocks, which are required to operate the AK4344, are MCLK, BICK and LRCK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the ...

Page 13

LRCK BICK(32fs SDTI( BICK(64fs) Don't Care SDTI(i) SDTI-15:MSB, 0:LSB LRCK BICK(64fs) Don't Care SDTI(i) 23:MSB, 0:LSB LRCK BICK(64fs SDTI(i) 23:MSB, 0:LSB ...

Page 14

De-emphasis Filter A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is ...

Page 15

Reset Function (1) Reset by RSTN bit When RSTN bit =0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage. Figure 15 shows the example of reset by RSTN ...

Page 16

RESET by MCLK stop (PDN pin = “H”) When MCLK stops, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage. PDN pin (1) Internal Power-down State D/A In Power-down ...

Page 17

Control Interface The AK4344 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”). 1.4-wire μ P I/F mode (MODE bit = “0”, default) The internal registers may be ...

Page 18

P I/F mode (MODE bit = “1”) Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed ...

Page 19

Register Map Addr Register Name 00H Control 1 01H Control 2 02H Control 3 Notes: For addresses from 03H to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. ...

Page 20

Addr Register Name D7 01H Control 2 0 R/W Default 0 DEM1-0: De-emphasis Response (Table 4) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal speed 01: Double speed 10: Half speed 11: Auto (default) When changing between Normal/Double Speed ...

Page 21

Figure 19 and Figure 20 shows the system connection diagram. The evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Master Clock 64fs 24bit Audio Data fs Reset & Power down Micro ...

Page 22

Grounding and Power Supply Decoupling The AK4344 requires careful attention for power supply and grounding arrangements. VDD is usually supplied from the analog supply in the system. System analog ground and digital ground should be connected together near to ...

Page 23

TSSOP (Unit: mm) *5.0 ± 0 0.22 ± 0.1 0.13 M Seating Plane NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: ...

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Date (YY/MM/DD) Revision 07/06/20 00 These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized ...

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