AK4359A AKM [Asahi Kasei Microsystems], AK4359A Datasheet

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AK4359A

Manufacturer Part Number
AK4359A
Description
106dB 192kHz 24-Bit 8ch DAC
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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The AK4359A is an eight channels 24bit DAC corresponding to digital audio system. Using AKM's
advanced multi bit architecture for its modulator the AK4359A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4359A has single end SCF outputs,
increasing performance for systems with excessive clock jitter. The AK4359A accepts 192kHz PCM data,
ideal for a wide range of applications including DVD-Audio.
MS1010-E-01
DZF
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
LOUT4
ROUT4
Sampling Rate Ranging from 8kHz to 192kHz
24Bit 8 times Digital Filter with Slow roll-off option
THD+N: -94dB
DR, S/N: 106dB
High Tolerance to Clock Jitter
Single Ended Output Buffer with 2nd order Analog LPF
Digital De-emphasis for 32, 44.1 & 48kHz sampling
Zero Detect function
Channel Independent Digital Attenuator (Linear 256 steps)
3-wire Serial and I
I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I
Master clock:
Power Supply: 4.5 to 5.5V
30pin VSOP Package
AK4384 Semi-compatible
AK4359 Compatible
LPF
LPF
LPF
LPF
LPF
LPF
LPF
LPF
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
SCF
SCF
SCF
SCF
SCF
SCF
SCF
SCF
256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode)
GENERAL DESCRIPTION
2
C Bus μP I/F for mode setting
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
FEATURES
- 1 -
DATT
DATT
DATT
DATT
DATT
DATT
DATT
DATT
106dB 192kHz 24-Bit 8ch DAC
Audio
PCM
I/F
Register
Control
AK4359A
AK4359A
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
SDTI4
3-wire
or I2C
2
S, TDM
[AK4359A]
2008/10

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AK4359A Summary of contents

Page 1

... The AK4359A is an eight channels 24bit DAC corresponding to digital audio system. Using AKM's advanced multi bit architecture for its modulator the AK4359A delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4359A has single end SCF outputs, increasing performance for systems with excessive clock jitter. The AK4359A accepts 192kHz PCM data, ideal for a wide range of applications including DVD-Audio ...

Page 2

... Ordering Guide -20 ∼ +85°C AK4359AEF -40 ∼ +105°C AK4359AVF AKD4359A Evaluation Board for AK4359A ■ Pin Layout MCLK BICK SD TI1 LRCK RST B SMUTE/C SN/CAD0 ACKS/CC LK/SCL DIF0/CDTI/SDA SD TI2 SDTI3 SDTI4 TDM0B DEM0 DVDD VSS1 MS1010-E-01 30pin VSOP 30pin VSOP ...

Page 3

... ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 INVL3 INVR3 INVL4 DEMA DEMB DEMC [AK4359A] D0 RSTN SMUTE 0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 INVR4 R4 R4 DEMD 2008/10 ...

Page 4

... Audio Serial Data Clock DAC1 Audio Serial Data Input L/R Clock Reset Mode When at “L”, the AK4359A is in the reset mode. The AK4359A must be reset once upon power-up. Soft Mute in parallel control mode “H”: Enable, “L”: Disable Chip Select in serial 3-wire mode ...

Page 5

... MS1010-E-01 Setting Leave open. Leave open. Connect to VSS1. Connect to DVDD or VSS1. ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD ΔGND (Note 2) IIN VINA VIND AK4359AEF Ta AK4359AVF Ta Tstg Symbol min AVDD 4.5 DVDD 4 [AK4359A] min max -0.3 6.0 -0.3 6.0 - 0.3 ±10 - -0.3 AVDD+0.3 -0.3 DVDD+0.3 -20 85 -40 105 -65 150 typ max 5.0 5.5 5.0 5.5 Units ...

Page 6

... DVSS. MS1010-E-01 ANALOG CHARACTERISTICS ≥5kΩ; unless otherwise specified) L min (Note 4) 0dBFS -60dBFS 0dBFS -60dBFS 0dBFS -60dBFS (Note 5) 98 (Note (Note 7) 3.15 (Note 8) 5 (Note [AK4359A] typ max Units 24 Bits -94 - 106 dB 106 dB 100 dB ...

Page 7

... Fs=192kHz FR - Symbol min 12 12 fs=44.kHz fs=96kHz FR - fs=192kHz CHARACTERISTICS Symbol min VIH 2.2 VIL - VOH DVDD-0.4 VOL - (Note 13) Iin - - 7 - [AK4359A] typ max Units 20.0 kHz 22.05 - kHz kHz ± 0. 19.3 - 1/fs + 0.06/-0. 0.06/-0. 0.06/-0. typ max Units 8.1 kHz 18.2 - kHz kHz ± 0.005 dB dB 19.3 - 1/fs +0.1/-4 ...

Page 8

... [AK4359A] min typ max Units 2.048 11.2896 36.864 MHz 120 192 3/256fs 3/256fs 8 48 ...

Page 9

... RSTB Pulse Width Note 14. BICK rising edge must not occur at the same time as LRCK edge. Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 16. The AK4359A can be reset by bringing the RSTB pin = “L”. 2 Note 17 registered trademark of Philips Semiconductors. ...

Page 10

... MCLK LRCK BICK LRCK BICK SDTI MS1010-E-01 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tBLR tLRB tSDS tSDH Audio Serial Interface Timing - 10 - [AK4359A] VIH VIL dCLK=tCLKH x fCLK, tCLKL x fCLK VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2008/10 ...

Page 11

... C1 C0 R/W WRITE Command Input Timing D2 D1 WRITE Data Input Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start Bus mode Timing tRST Reset Timing - 11 - [AK4359A] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH D0 VIL VIH VIL tSP VIH ...

Page 12

... DFS1-0 bits. In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4359A operates by Normal Speed Mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does not support 128fs and 192fs of double speed mode ...

Page 13

... Table 5. Sampling Speed (Auto Setting Mode) MCLK (MHz) 256fs 384fs - - 16.3840 - - 22.5792 - - 24.5760 22.5792 33.8688 24.5760 36.8640 - - - - - 13 - BICK 384fs 64fs 5.6448MHz 6.1440MHz BICK 64fs 106896MHz 12.2880MHz Double Quad 512fs 768fs 1152fs 24.5760 36.8640 33.8688 - 36.8640 - - - - - - - - - - - - - [AK4359A] Sampling Speed Normal Double Quad 2008/10 ...

Page 14

... Figure 6 LRCK BICK ≥32fs H/L ≥40fs H/L ≥48fs H/L 2 ≥48fs S Compatible L/H ≥48fs H/L ↑ 256fs 2 ↓ S Compatible 256fs ↑ 256fs ↑ 128fs 2 ↓ S Compatible 128fs ↑ 128fs [AK4359A] Table 8 can Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 2008/10 ...

Page 15

... Figure 3. Mode 2 Timing - Rch Data Rch Data Don’t care 1 Rch Data [AK4359A 2008/10 ...

Page 16

... BICK 32 BICK 32 BICK 3/256fs (min BICK 32 BICK 32 BICK 3/256fs (min BICK 32 BICK 32 BICK [AK4359A 2008/10 ...

Page 17

... BICK 32 BICK BICK 32 BICK 3/128fs (min BICK 32 BICK BICK 32 BICK 3/128fs (min BICK 32 BICK BICK 32 BICK [AK4359A 2008/10 ...

Page 18

... Output Volume Control The AK4359A includes channel independent digital output volume control (ATT) with 256 levels at linear step including MUTE. The volume control is in front of the DAC, and it can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition time of 1 level and all 256 levels is shown in (ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “ ...

Page 19

... DZF pin is fixed to “L” regardless of the state of the SMUTE pin. Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”) MS1010-E-01 (Table 10) from the current ATT level. When the SMUTE bit (1) GD (2) (4) 8192/fs (Table 10). For this example, in Normal Speed Mode, the time is 1020LRCK - 19 - [AK4359A] (1) (3) GD 2008/10 ...

Page 20

... System Reset The AK4359A should be reset once by bringing the RSTB pin = “L” upon power-up. The AK4359A is powered up and the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4359A is in the power-down mode until MCLK and LRCK are input. ...

Page 21

... RSTN bit “1”. (6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance MS1010-E-01 3~4/fs (5) D igital Block P d “0 ” data GD (3) (2) (6) Figure 13. Reset Sequence Example (DZFB bit = “0” [AK4359A] 2~3/fs (5) Normal O peration GD (1) (3) 2/ fs(4) 2008/10 ...

Page 22

... Reset Function (MCLK, BICK and LRCK stop) When the MCLK, LRCK or BICK stops, the digital circuit of the AK4359A is placed in power-down mode. When the MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4359A returns to normal operation mode. AVDD pin ...

Page 23

... Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4359A latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The clock speed of CCLK is 5MHz (max). ...

Page 24

... HIGH defines a STOP condition (Figure The AK4359A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4359A generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH prior to generating the stop condition, the address counter will “ ...

Page 25

... MASTER S START CONDITION SDA SCL MS1010-E-01 S Figure 20. START and STOP conditions 2 1 Figure 21. Acknowledge on the I data line change stable; of data data valid allowed Figure 22. Bit transfer on the stop condition not acknowledge acknowledge 8 clock pulse for acknowledgement 2 C-bus 2 C-bus [AK4359A] 9 2008/10 ...

Page 26

... ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 INVL3 INVR3 INVL4 DEMA DEMB DEMC DIF1 DIF0 PW1 [AK4359A] D0 RSTN SMUTE 0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 INVR4 R4 R4 DEMD D0 RSTN 1 2008/10 ...

Page 27

... Normal Speed 1 128fs fixed 1-2 Normal, Double Speed SLOW DFS1 (Table 9) (Table PW4 PW3 PW2 Sampling Speed DFS0 DEM1 DEM0 DZFB PW1 [AK4359A] D0 SMUTE 2008/10 ...

Page 28

... [AK4359A ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...

Page 29

... AK4359A 7 ACKS ROUT1 8 DIF0 P/S SDTI2 9 LOUT2 ROUT2 10 SDTI3 LOUT3 11 SDTI4 TDM0 12 ROUT3 DEM0 13 LOUT4 ROUT4 14 DVDD DVSS 15 DEM1 0. [AK4359A] 30 Mute Signal 29 0.1u 10u Analog 0.1u 10u 25 MUTE L1ch Out 10u R1ch Out 24 MUTE 23 22 L2ch Out MUTE 21 MUTE R2ch Out 20 MUTE ...

Page 30

... AK4359A 7 CCLK ROUT1 8 CDTI P/S SDTI2 9 LOUT2 10 SDTI3 ROUT2 11 SDTI4 LOUT3 12 TDM0 ROUT3 13 DEM0 LOUT4 14 ROUT4 DVDD DVSS 15 I2C 0. [AK4359A 0.1u 10u Analog 10u 0.1u 10u 25 L1ch Out MUTE 10u R1ch Out 24 MUTE 23 22 L2ch Out MUTE 21 R2ch Out MUTE 20 MUTE ...

Page 31

... Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4359A must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor, especially 0.1μ ...

Page 32

... VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS1010-E-01 PACKAGE 16 15 0.65 Detail A 0.08 Epoxy Cu Solder (Pb free) plate - 32 - [AK4359A] 1.5MAX A +0.10 0.15 -0.05 2008/10 ...

Page 33

... MS1010-E-01 MARKING (AK4359AEF) AKM AK4359AEF XXXXXXXXX XXXXXXXXX Date code identifier MARKING (AK4359AVF) AKM AK4359AVF XXXXXXXXX XXXXXXXXX Date code identifier - 33 - [AK4359A] 2008/10 ...

Page 34

... MS1010-E-01 REVISION HISTORY Reason Page Contents First Edition Spec Addition AK4359AVF was added. IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK4359A] in any safety, life support, or Note1) ...

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