AK4371VN AKM [Asahi Kasei Microsystems], AK4371VN Datasheet

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AK4371VN

Manufacturer Part Number
AK4371VN
Description
DAC with built-in PLL & HP-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet

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AK4371VN-L
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ASAHI
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AK4371VN-L
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The AK4371 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is
synchronized to typical mobile phone clock frequencies. The AK4371 features an analog mixing circuit
that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of
power into 16Ω. The AK4371 is packaged in a 32-pin QFN (4mm×4mm) package, ideal for portable
applications.
MS0596-E-00
Multi-bit ΔΣ DAC
Sampling Rate
On chip perfect filtering 8 times FIR interpolator
Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
System Clock
Audio I/F Format: MSB First, 2’s Complement
Digital Mixing: LR, LL, RR, (L+R)/2
Bass Boost Function
Digital ATT
Analog Mixing Circuit: 6 Inputs (Single-ended or Full-differential)
Stereo Lineout
Mono Hands-free Output
Headphone Amplifier
μ P Interface: 3-wire/I
Power Supply: 1.6V ∼ 3.6V
Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output)
Ta: − 30 ∼ 85°C
Small Package: 32pin QFN (4mm x 4mm, 0.4mm pitch)
Register Compatible with AK4368
- Output Power: 0.8mW @ 600Ω 3.3V
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
- 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
- Input Level: AC Couple Input Available
- I
- Master/Slave Mode
- S/N: 90dB@3.3V
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
- Output Power: 40mW x 2ch @16Ω, 3.3V
- S/N: 92dB@3.3V
- Pop Noise Free at Power-ON/OFF and Mute
- Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain
2
S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB)
GENERAL DESCRIPTION
2
C
14.4MHz, 13MHz, 12MHz and 11.2896MHz
FEATURE
DAC with built-in PLL & HP-AMP
- 1 -
AK4371
[AK4371]
2007/04

Related parts for AK4371VN

AK4371VN Summary of contents

Page 1

The AK4371 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is synchronized to typical mobile phone clock frequencies. The AK4371 features an analog mixing circuit that allows easy interfacing in mobile phone and ...

Page 2

Block Diagram PVDD VSS3 MCKO BICK Audio LRCK Interface SDATA DVDD VSS2 Digital Volume emphasis Bass Digital Boost PDN I2C CAD0/CSN Serial I/F SCL/CCLK SDA/CDTI MS0596-E-00 MCKI VCOC LIN2 LIN1/IN− PLL DAC (Lch) De- Filter DAC (Rch) RIN1/IN+ RIN2 ...

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... Ordering Information −30 ∼ +85°C AK4371VN AKD4371 Evaluation board for AK4371 ■ Pin Layout HPR 25 HPL 26 RIN2 27 LIN2 28 RIN3 29 LIN3 30 RIN1/IN LIN1/IN− MS0596-E-00 32pin QFN (0.4mm pitch) AK4371VN Top View - 3 - [AK4371] MUTET 16 I2C 15 PDN 14 CSN/CAD0 13 CCLK/SCL 12 CDTI/SDA 11 MCKO 10 VSS3 9 2007/04 ...

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Comparison with AK4368 1 Function Function Analog Mixing PLL Reference Clock MCKI at EXT Mode Internal VREF Handsfree Amp HP-Amp Output Volume HP-Amp Hi-Z Setting 3D Enhancement ALC Package 2 Register (difference from AK4368) Addr Register Name 00H Power ...

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No. Pin Name I/O 1 SDATA I Audio Serial Data Input Pin 2 BICK I/O Audio Serial Data Clock Pin 3 LRCK I/O Input / Output Channel Clock Pin 4 MCKI I External Master Clock Input Pin Digital Power Supply ...

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Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name LOUT, ROUT, MOUT, MUTET, HPR, HPL, RIN3, Analog LIN3, RIN2, LIN2, RIN1/IN+, LIN1/IN− Digital MCKI MCKO (VSS1, VSS2, VSS3=0V; Note 2, Note ...

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AVDD=PVDD=DVDD=HVDD=2.4V, VSS1=VSS2=VSS3=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with R =16Ω and C L Parameter DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 8) Analog ...

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Parameter Mono Handsfree Output: (MOUT pin, R Analog Output Characteristics: THD+N (0dBFS Output) S/N A-weighted, 2.4V A-weighted, 3.3V DC Accuracy Gain Drift Load Resistance (Note 9) Load Capacitance Output Voltage (0dBFS Output) (Note 14) Output Volume: (MOUT pin) Step Size ...

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Parameter LINEIN: (LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 pins) Analog Input Characteristics Input Resistance (Figure 25, Figure 26, Figure 27, Figure 28) LIN1 pin LIN1HL=LIN1HR=LIN1L=LIN1R=LIN1M bits = “1” LIN1HL bit = “1”, LIN1HR=LIN1L=LIN1R=LIN1M bits = “0” LIN1HR bit = “1”, LIN1HL=LIN1L=LIN1R=LIN1M bits = “0” LIN1L ...

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Parameter Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 15) AVDD+PVDD+DVDD HVDD Power-Down Mode (PDN pin = “L”) (Note 16) Note 15. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, PMMO=MCKO bits = “0”, HP-Amp no ...

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AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = “OFF”) Parameter DAC Digital Filter: (Note 17) Passband (Note 18) Stopband (Note 18) Passband Ripple Stopband Attenuation Group Delay (Note 19) Group Delay Distortion DAC Digital Filter + Analog Filter: ...

Page 12

AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V) Parameter High-Level Input Voltage 2.2V≤DVDD≤3.6V 1.6V≤DVDD<2.2V Low-Level Input Voltage 2.2V≤DVDD≤3.6V 1.6V≤DVDD<2.2V Input Voltage at AC Coupling (Note 23) High-Level Output Voltage Low-Level Output Voltage (Except SDA pin: Iout=200μA) (SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA) (SDA ...

Page 13

AVDD, DVDD, PVDD, HVDD=1.6 ∼ 3.6V; C Parameter Master Clock Input Timing Frequency (PLL mode) (EXT mode) Pulse Width Low (Note 24) Pulse Width High (Note 24) AC Pulse Width (Note 25) LRCK Timing Frequency Duty Cycle: Slave Mode ...

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Parameter 2 Control Interface Timing (I C Bus mode): (Note 29) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition ...

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Timing Diagram 1000pF MCKI Input MCKI LRCK BICK MCKO MS0596-E-00 Measurement Point 100kΩ VSS2 VSS2 Figure 3. MCKI AC Coupling Timing 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL tH tL dMCK=tH/(tH+tL) or tL/(tH+tL) Figure 4. Clock Timing - 15 ...

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LRCK tBLR BICK SDATA LRCK tMBLR BICK SDATA MS0596-E-00 tLRB tSDS tSDH Figure 5. Serial Interface Timing (Slave Mode) tSDS Figure 6. Serial Interface Timing (Master mode [AK4371] VIH VIL VIH VIL VIH VIL 50%DVDD 50%DVDD tSDH ...

Page 17

CSN CCLK CDTI CSN CCLK CDTI SDA tBUF tLOW SCL tHD:STA Stop Start PDN MS0596-E-00 tCSS tCCKL tCCKH tCDS tCDH C1 C0 R/W Figure 7. WRITE Command Input Timing Figure 8. WRITE Data Input Timing tR tHIGH ...

Page 18

System Clock There are the following six clock modes to interface with external devices (Table 1 and Table 2). Mode PLL Master Mode PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: ...

Page 19

PLL Mode (PMPLL bit = “1”) When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL ...

Page 20

When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits. (Table 6) Mode FS3 bit Others Table 6. Setting of Sampling Frequency ...

Page 21

PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by ...

Page 22

PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4371 is generated by an internal ...

Page 23

PLL reference clock: LRCK pin Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6). AK4371 Figure 14. PLL Slave Mode (PLL Reference Clock: LRCK pin) MS0596-E-00 MCKI MCKO 32fs ∼ 64fs BCLK BICK 1fs LRCK ...

Page 24

EXT Mode (PMPLL bit = “0”: Default) The AK4371 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the master clock can directly input to the DAC via the ...

Page 25

Mode FS3 FS2 Others Others Table 11. ...

Page 26

Serial Data Interface The AK4371 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available, selected by setting the DIF2, DIF1 and DIF0 bits (Table 16). Mode 0 is compatible with existing 16-bit ...

Page 27

LRCK BICK SDATA 16bit SDATA 20bit SDATA 24bit Figure 19. Mode 2 Timing (LRP = BCKP bits = “0”) LRCK BICK SDATA 15 14 16bit SDATA 19 18 20bit SDATA 23 ...

Page 28

Digital Attenuator The AK4371 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 17). At ...

Page 29

Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ during the ATT_DATA×ATT transition time (Table 18) from the current ATT level. When the ...

Page 30

De-emphasis Filter The AK4371 includes a digital de-emphasis filter (tc = 50/15μs), using an IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 19). DEM1 bit ■ ...

Page 31

Headphone Output (HPL, HPR pins) The power supply voltage for the headphone-amp is supplied from the HVDD pin and is centered on the MUTET voltage. The headphone-amp output load resistance is 16Ω (min). When the MUTEN bit is “1” ...

Page 32

External Circuit of Headphone-Amp > The cut-off frequency of the headphone-amp output depends on the external resistor and capacitor used. Table 23 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R ...

Page 33

Analog Mixing Circuit for Headphone Output > DALHL, LIN1HL, RIN1HL, LIN2HL, RIN2HL, LIN3HL and RIN3HL bits control each path switch of HPL output. DARHR, LIN1HR, RIN1HR, LIN2HR, RIN2HR, LIN3HR and RIN3HR bits control each path switch of HPR output. ...

Page 34

Headphone Output Volume HPL/HPR volume is controlled by ATTH4-0 bit when HMUTE bit = “0” (+12dB ∼ −51dB or +6dB ∼ −57dB or 0dB ∼ −63dB, 1.5dB or 3dB step, Table 25) HPG1-0 bits = “10” HMUTE ATTH4-0 (DAC ...

Page 35

Stereo Line Output (LOUT, ROUT pins) The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line output is powered-up. DALL, LIN1L, RIN1L, LIN2L, RIN2L, LIN3L and RIN3L bits ...

Page 36

Analog Mixing Circuit of Full-differential Mono input > When LDIF=LIN1L=RIN1R bits = “1”, LIN1 and RIN1 pins becomes IN− and IN+ pins, respectively. IN− and IN+ pins can be used as full-differential mono line input for analog mixing of ...

Page 37

Mono Hands-free Output (MOUT pin) The common voltage is 0.475 x AVDD. The load resistance is 600Ω(min). When the PMMO bit is “1”, the mono Hands-free output is powered-up. DALM, DARM, LIN1M, RIN1M, LIN2M, RIN2M, LIN3M and RIN3M bits ...

Page 38

Power-Up/Down Sequence (EXT mode) 1) DAC → HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care (3) Clock Input PMDAC bit DAC Internal PD State SDTI pin DALHL, (4) >0s DARHR bits PMHPL, PMHPR bits ...

Page 39

DAC → Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Clock Input Don’t care PMDAC bit DAC Internal PD(Power-down) State SDTI pin DALL, (3) >0s DARR bits PMLO bit ATTL/R7-0 bits 00H(MUTE) LMUTE, 10H(MUTE) ATTS3-0 bits ...

Page 40

DAC → MOUT Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Clock Input Don’t care PMDAC bit DAC Internal PD(Power-down) State SDTI pin DALM, (3) >0s DARM bits PMMO bit ATTL/R7-0 bits 00H(MUTE) MMUTE, 10H(MUTE) ATTM3-0 bits ...

Page 41

LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LIN1HL, LIN2HL, LIN3HL RIN1HR, RIN2HR, RIN3HL bits PMHPL/R bits MUTEN bit LIN1/RIN1/ LIN2/RIN2/ (Hi-Z) LIN3/RIN3 pins HPL/R pins Figure 32. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and HP-Amp ...

Page 42

LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LIN1L, RIN1R, LIN2L, RIN2R, LIN3L, RIN3R bits PMLO bit LIN1/RIN1/ (Hi-Z) LIN2/RIN2/ LIN3/RIN3 pins LMUTE, 10H(MUTE) ATTS3-0 bits LOUT/ROUT pins (Hi-Z) Figure 33. Power-up/down sequence of ...

Page 43

LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 → MOUT Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit LIN1M, RIN1M, LIN2M, RIN2M, LIN3M, RIN3M bits PMMO bit LIN1/RIN1/ (Hi-Z) LIN2/RIN2/ LIN3/RIN3 pins MMUTE, 10H(MUTE) ATTM3-0 bits MOUT pin (Hi-Z) Figure 34. Power-up/down sequence of ...

Page 44

Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written to via the 3-wire μP interface pins (CSN, CCLK and CDTI). The data on this interface consists of the Chip address (2-bits, ...

Page 45

I C-bus Control Mode (I2C pin = “H”) The AK4371 supports fast-mode I (2)-1. WRITE Operations Figure 36 shows the data transfer sequence for the I HIGH to LOW transition on the SDA line while SCL is HIGH ...

Page 46

READ Operations Set the R/W bit = “1” for the READ operation of the AK4371. After a transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the writing cycle after ...

Page 47

SDA SCL start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0596-E-00 S Figure 42. START and STOP Conditions 2 1 Figure 43. Acknowledge on the I data line change stable; ...

Page 48

Register Map Addr Register Name 00H Power Management 0 01H PLL Control 02H Clock Control 03H Mode Control 0 04H Mode Control 1 05H DAC Lch ATT 06H DAC Rch ATT 07H Headphone Out Select 0 08H Lineout Select ...

Page 49

Register Definitions Addr Register Name 00H Power Management 0 R/W Default PMVCM: Power Management for VCOM Block 0: Power OFF (default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (default) 1: Power ON When the ...

Page 50

Addr Register Name 01H PLL Control R/W Default FS3-0: Select Sampling Frequency PLL mode: Table 5 EXT mode: Table 11 PLL4-0: Select PLL Reference Clock PLL mode: Table 4 EXT mode: PLL4-0 bits are disabled (PLL4 bit is D7 bit ...

Page 51

Addr Register Name 03H Mode Control 0 R/W Default DIF2-0: Audio Data Interface Format Select (Table 16) Default: “010” (Mode 2) LRP: LRCK Polarity Select in Slave Mode 0: Normal (default) 1: Invert BCKP: BICK Polarity Select in Slave Mode ...

Page 52

Addr Register Name 05H DAC Lch ATT 06H DAC Rch ATT R/W Default ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 17) ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 17) Default: ...

Page 53

Addr Register Name 08H Lineout Select 0 R/W Default DALL: DAC left channel output is added to the LOUT buffer amp. 0: OFF (default DARR: DAC right channel output is added to the ROUT buffer amp. 0: OFF ...

Page 54

Addr Register Name 0DH Headphone Out Select R/W Default RIN1HL: RIN1 signal is added to the left channel of the Headphone-Amp 0: OFF (default LIN1HR: LIN1 signal is added to the right channel of the Headphone-Amp 0: OFF ...

Page 55

Addr Register Name 0FH Lineout Select R/W Default RIN1L: RIN1 signal is added to the left channel of the Lineout 0: OFF (default LIN1R: LIN1 signal is added to the right channel of the Lineout 0: OFF (default) ...

Page 56

Addr Register Name 10H Mono Mixing R/W Default L1HM: LIN1/RIN1 signal is added to Headphone-Amp as (L+R)/2. 0: OFF (default L1M: LIN1/RIN1 signal is added to LOUT/ROUT as (L+R)/2. 0: OFF (default L2HM: LIN2/RIN2 signal is ...

Page 57

Addr Register Name 12H MOUT Select R/W Default DALM: DAC left channel output signal is added to MOUT 0: OFF (default DARM: DAC right channel output signal is added to MOUT 0: OFF (default LIN1M: LIN1 ...

Page 58

Addr Register Name 13H MOUT ATT R/W Default ATTM3-0: Setting of the attenuation value of output signal from MOUT (Table 27) Default: MMUTE bit = “1”, ATTM3-0 bits = “0000” (MUTE) Setting of ATTM3-0 bits is enabled at HMUTE bit ...

Page 59

... When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be connected between DVDD and the ground. Figure 45. Typical Connection Diagram (In case of AC coupling to MCKI) MS0596-E-00 SYSTEM DESIGN Handsfree 0.1µ 0.22µ 2.2µ 0.1µ HPR 26 HPL 27 RIN2 AK4371VN 28 LIN2 29 RIN3 Top View 30 LIN3 31 RIN1 32 LIN1 10 Audio Controller - 59 - Speaker SPK-Amp ...

Page 60

Note: If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM voltage (= 0.475 x AVDD) externally. Figure 46. External Bias Circuit Example for ...

Page 61

QFN (Unit: mm) 4.0 ± 0 0.08 0.4 Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Package & Lead frame material Package molding compound: Epoxy ...

Page 62

Date (YY/MM/DD) Revision 07/04/13 00 These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized ...

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