WM8951L_07 WOLFSON [Wolfson Microelectronics plc], WM8951L_07 Datasheet
WM8951L_07
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WM8951L_07 Summary of contents
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Stereo ADC with Microphone Input and Clock Generator DESCRIPTION The WM8951L is a low power stereo ADC with an integrated microphone interface and crystal oscillator for clock generation. The WM8951L is ideal for voice recorders, wireless microphones and games ...
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WM8951L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6 TERMINOLOGY .....................................................................................................7 POWER CONSUMPTION ......................................................................................8 MASTER CLOCK TIMING......................................................................................9 DIGITAL AUDIO INTERFACE – MASTER ...
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Production Data PIN CONFIGURATION ORDERING INFORMATION TEMPERATURE DEVICE RANGE o WM8951LGEFL - WM8951LGEFL/R -25 to +85 C Note: Reel quantity = 3,500 w AVDD PACKAGE RANGE 28-lead QFN 1.8 to 3.6V (lead free) 28-lead QFN 1.8 ...
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WM8951L PIN DESCRIPTION PIN NAME 1 XTI/MCLK Digital Input 2 XTO Digital Output 3 DCVDD 4 DGND 5 DBVDD 6 CLKOUT Digital Output 7 BCLK Digital Input/Output 8 TP1 9 TP2 10 ADCDAT Digital Output 11 ADCLRC Digital Input/Output 12 ...
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Production Data ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
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WM8951L ELECTRICAL CHARACTERISTICS Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND1, AGND2 = 0V, DCVDD = 1.5V, DGND = 0V, T XTI/MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Output ...
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Production Data Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND1, AGND2 = 0V, DCVDD = 1.5V, DGND = 0V, T XTI/MCLK = 256fs unless otherwise stated. Microphone Input to ADC @ 0dB Gain 48kHz (40kΩ Source Impedance. See ...
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WM8951L POWER CONSUMPTION MODE DESCRIPTION Record Line Record oscillator enabled Mic Record oscillator enabled Standby Clock stopped 0 1 Power Down Clock stopped 1 1 Table 1 Powerdown Mode Current Consumption Examples Notes: 1. AVDD, AVDD2, ...
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Production Data MASTER CLOCK TIMING XTI/MCLK Figure 1 System Clock Timing Requirements Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T 256fs unless otherwise stated. PARAMETER System Clock Timing Information XTI/MCLK System ...
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WM8951L DIGITAL AUDIO INTERFACE – MASTER MODE WM8951L ADC Figure 3 Master Mode Connection BCLK (Output) ADCLRC (Output) ADCDAT Figure 4 Digital Audio Data Timing – Master Mode Test Conditions AVDD1, AVDD2, DBDD = 3.3V, AGND = 0V, DCVDD = ...
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Production Data DIGITAL AUDIO INTERFACE – SLAVE MODE BCLK WM8951 ADCLRC ADC ADCDAT Figure 5 Slave Mode Connection BCLK ADCLRC ADCDAT Figure 6 Digital Audio Data Timing – Slave Mode Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, ...
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WM8951L MPU INTERFACE TIMING CSB SCLK SDIN Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T 256fs unless otherwise stated. ...
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Production Data t 3 SDIN SCLK t 1 Figure 8 Program Register Input Timing – 2-Wire MPU Serial Control Mode Test Conditions AVDD1, AVDD2, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T 256fs unless otherwise ...
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WM8951L DEVICE DESCRIPTION INTRODUCTION The WM8951L is a low power stereo audio ADC designed specifically for portable audio products. It’s features, performance and low power consumption make it ideal for portable voice recorders, games console accessories and wireless microphones. The ...
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Production Data LINEIN Figure 9 Line Input Schematic The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in 1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD1/2 ...
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WM8951L The line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces ...
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Production Data st The 1 stage comprises a nominal gain 50k/10k = 5. By adding an external resistor (Rmic) in series with MICIN the gain of stage can be adjusted. For example adding Rmic = 40K sets ...
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WM8951L Recommended component values are C1 = 220pF (npo ceramic 1µ 680 ohms 47k. Rmic values depends on gain setting (see above). R1 and R2 form part of the biasing network (refer to Microphone ...
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Production Data The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will ...
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WM8951L DEVICE OPERATION DEVICE RESETTING The WM8951L contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the ...
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Production Data Cp Figure 16 Crystal Oscillator Application Circuit The WM8951L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio ADCs, regardless of the converter architecture. The WM8951L architecture is ...
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WM8951L The digital audio interface takes the data from the internal ADC digital filter and places it on the ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels ...
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Production Data Figure 19 Right Justified Mode DSP mode is where the left channel MSB is available on either the 1 (selectable by LRP) following a LRC transition high. Right channel data immediately follows left channel data. Figure 20 DSP ...
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WM8951L The ADC digital audio interface modes are software configurable as indicated in Table 8. Note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended. The length of the digital ...
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Production Data WM8951 ADC Figure 21 Master Mode As a slave device the WM8951L sequences the data transfer (ADCDAT) over the digital audio interface in response to the external applied clocks (BCLK, ADCLRC). This is illustrated in Figure 22. WM8951 ...
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WM8951L Sample rates listed in the following sections are supported. REGISTER ADDRESS 0001000 Sampling Control Table 11 Sample Rate Control NORMAL MODE SAMPLE RATES In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ...
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Production Data SAMPLING RATE kHz 44.1 (Note 1) 88.2 Table 12 Normal Mode Sample Rate Look-up Table Notes not exact, actual = 8.018kHz 2. All other combinations of BOSR and SR[3:0] that are not in the truth table ...
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WM8951L The exact sample rates achieved are defined by the relationships in Table 13 below. TARGET SAMPLING RATE kHz 8 32 44.1 48 88.2 96 Table 13 Normal Mode Actual Sample Rates 128/192fs NORMAL MODE The Normal Mode sample rates ...
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Production Data USB MODE SAMPLE RATES In USB mode the MCLK/crystal oscillator input is 12MHz only. SAMPLING RATE ADC kHz 44.1 (Note 2) (Note 1) 88.2 (Note 3) Table 15 USB Mode Sample Rate Look-up Table Notes not ...
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WM8951L The exact sample rates supported for all combinations are defined by the relationships in Table 16 below. TARGET SAMPLING RATE kHz 8 32 44.1 48 88.2 96 Table 16 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO ...
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Production Data 3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE The WM8951L can be controlled using a 3-wire serial interface. SDIN is used for the program data, SCLK is used to clock in the program data and CSB is use to latch ...
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WM8951L The controller will then send the remaining eight data bits (bits B7-B0) and the WM8951L will then acknowledge again by pulling SDIN low. A stop condition is defined when there is a low to high transition on SDIN while ...
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Production Data OSCPD: Powers off the on board crystal oscillator. The MCLK input will function independently of the Oscillator being powered down. CLKOUTPD: Powers down the CLOCKOUT pin. This conserves power, reduces digital noise and RF emissions if not required. ...
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WM8951L REGISTER MAP The complete register map is shown in Table 23. The detailed description can be found in Table 24 and in the relevant text of the device description. There are 11 registers with 16 bits per register (7 ...
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Production Data REGISTER ADDRESS 0000000 Left Line In 0000001 Right Line In 0000100 Analogue Audio Path Control 0000101 Digital Audio Path Control 0000110 Power Down Control w BIT LABEL DEFAULT 4:0 LINVOL[4:0] 10111 ( 0dB ) 7 LINMUTE 1 8 ...
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WM8951L REGISTER ADDRESS 0000111 Digital Audio Interface Format 0001000 Sampling Control 0001001 Active Control 0001111 Reset Register Table 24 Register Map Description w BIT LABEL DEFAULT 5 OSCPD 0 6 CLKOUTPD 0 7 POWEROFF 1 1:0 FORMAT[1:0] 10 3:2 IWL[1:0] ...
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Production Data DIGITAL FILTER CHARACTERISTICS The ADC employs different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the responses ...
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WM8951L ADC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 25 ADC Digital Filter Frequency Response –Type 0 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 27 ADC ...
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Production Data 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 31 ADC Digital Filter Frequency Response –Type 3 ADC HIGH PASS FILTER The WM8951L has a selectable digital high pass filter to remove DC offsets. ...
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WM8951L APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 33 External Components Diagram w Production Data PD Rev 4.1 December 2007 40 ...
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Production Data PACKAGE DIMENSIONS FL: 28 PIN QFN PLASTIC PACKAGE 5 CORNER D2 TIE BAR B D2 EXPOSED 6 GROUND PADDLE BOTTOM VIEW (A3 SEATING PLANE ...
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... Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon ...