WM8980CGEFL/RV WOLFSON [Wolfson Microelectronics plc], WM8980CGEFL/RV Datasheet
WM8980CGEFL/RV
Related parts for WM8980CGEFL/RV
WM8980CGEFL/RV Summary of contents
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Stereo CODEC with Speaker Driver and Video Buffer DESCRIPTION The WM8980 is a low power, high quality stereo CODEC with integrated video buffer designed for portable applications such as multimedia phone, digital still camera or digital camcorder. The device ...
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WM8980 DESCRIPTION ....................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 FEATURES ............................................................................................................ 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS ..................................................... ...
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Pre-Production 5-BAND EQUALISER .................................................................................................. 116 APPLICATION INFORMATION ......................................................................... 120 RECOMMENDED EXTERNAL COMPONENTS ......................................................... 120 PACKAGE DIAGRAM ....................................................................................... 121 IMPORTANT NOTICE ....................................................................................... 122 ADDRESS: .................................................................................................................. 122 REVISION HISTORY ......................................................................................... 123 w WM8980 PP, Rev 3.8, May 2012 ...
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... WM8980 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8980CGEFL/V -25C to +85C WM8980CGEFL/RV -25C to +85C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 40-lead QFN ( mm) MSL3 (Pb-free) 40-lead QFN ( mm) MSL3 (Pb-free, tape and reel) Pre-Production ...
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Pre-Production PIN DESCRIPTION PIN NAME TYPE 1 L2/GPIO2 Analogue input 2 RIP Analogue input Analogue input 3 RIN 4 R2/GPIO3 Analogue input 5 VBGND Supply 6 VBIN Analogue input Analogue output 7 VBREF 8 VBOUT Analogue output 9 VBVDD Supply ...
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WM8980 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Pre-Production ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, T otherwise stated. PARAMETER SYMBOL Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2) Full-scale Input Signal Level – V note this changes in proportion to AVDD (Note 1) Mic PGA ...
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WM8980 Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, T otherwise stated. PARAMETER SYMBOL Automatic Level Control (ALC) Target Record Level Programmable gain Gain Hold Time (Note 3,5) t HOLD Gain Ramp-Up (Decay) Time t DCY (Note 4,5) Gain Ramp-Down (Attack) Time ...
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Pre-Production Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, T otherwise stated. PARAMETER SYMBOL Speaker Output (LOUT2, ROUT2 with 8 bridge tied load, INVROUT2=1) Full scale output voltage, 0dB gain. (Note 9) Output Power P Total Harmonic Distortion THD Signal to Noise ...
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WM8980 Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD=VBVDD = 3.3V, T otherwise stated. PARAMETER SYMBOL Digital Input / Output Input HIGH Level V Input LOW Level V Output HIGH Level V Output LOW Level V Input capacitance Input leakage TERMINOLOGY 1. Input level ...
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Pre-Production SPEAKER OUTPUT THD VERSUS POWER Speaker Power vs THD+N (8Ohm BTL Load) AVDD=SPKVDD=DBVDD=3.3, DCVDD=1.8 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.00 50.00 100.00 150.00 200.00 Output Power (mW) Speaker Power vs THD+N (8Ohm BTL ...
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WM8980 POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE Off Sleep (VREF maintained, no clocks) 2 MIC Record (8kHz) Stereo 16Ω HP Playback (48kHz, quiescent) Stereo 16Ω HP Playback (48kHz, white noise) Stereo 16Ω HP Playback ...
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Pre-Production Estimated supply current for the analogue blocks is shown in Table 2. Note that power dissipated in the load is not shown. REGISTER BIT BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL ROUT1EN LOUT1EN BOOSTENR BOOSTENL INPPGAENR INPPGAENL ADCENR ...
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WM8980 AUDIO PATHS OVERVIEW w Pre-Production PP, Rev 3.8, May 2012 14 ...
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Pre-Production SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER SYMBOL System Clock Timing Information MCLK cycle time MCLK duty cycle T Note 1: PLL pre-scaling and PLL N ...
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WM8980 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge ...
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Pre-Production CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = 256fs, ...
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WM8980 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low ...
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Pre-Production INTERNAL POWER ON RESET CIRCUIT Figure 6 Internal Power on Reset Circuit Schematic The WM8980 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used reset the digital logic into a default state after power up. ...
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WM8980 Figure 8 Typical Power up Sequence where DVDD is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When AVDD ...
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Pre-Production DEVICE DESCRIPTION INTRODUCTION The WM8980 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, stereo digital camcorders, ...
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WM8980 OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a mono mix of left and right ...
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Pre-Production Stereo Camcorder; The provision of two stereo microphone preamplifiers, allows support for both internal and external microphones. All drivers for speaker, headphone and line output connections are integrated. The selectable ‘application filters’ after the ADC provide for features such ...
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WM8980 The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER ADDRESS R2 Power Management 2 Table 4 Input PGA Enable Register Settings REGISTER ADDRESS R44 Input Control Table 5 Input PGA Control INPUT PGA VOLUME CONTROLS The input ...
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Pre-Production REGISTER ADDRESS R45 Left channel input PGA volume control R46 Right channel input PGA volume control R32 ALC control 1 Table 6 Input PGA Volume Control w BIT LABEL DEFAULT 5:0 INPPGAVOLL 010000 Left channel input PGA volume 000000 ...
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WM8980 VOLUME UPDATES Volume settings will not be applied to the PGAs until a ‘1’ is written to one of the INPPGAUPDATE bits. This is to allow left and right channels to be updated at the same time, as shown ...
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Pre-Production Figure 12 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8980 will automatically update the volume. The volume updates will occur between one and two timeout ...
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WM8980 AUXILLIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs ‘beep’ input signal to be mixed with the outputs. The AUXL/R inputs ...
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Pre-Production The Auxiliary amplifier path to the BOOST stages is controlled by the AUXL2BOOSTVOL[2:0] and AUXR2BOOSTVOL[2:0] register bits. When AUXL2BOOSTVOL/AUXR2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps ...
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WM8980 The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 Table 9 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing ...
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Pre-Production ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8980 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional ...
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WM8980 SELECTABLE HIGH PASS FILTER A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of ...
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Pre-Production PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. The coefficients must be entered in 2’s complement notation. A0 and a1 are represented ...
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WM8980 Fc = 1000 100 48000 Hz 1 tan( 1 tan( a ...
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Pre-Production INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8980 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...
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WM8980 REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 8 ALCZC 0 ALC Zero Cross Control 0 = ALCZC off 1 = ALCZC on (only valid when ALCMODE=0. ALCZC should not be used when ALCMODE=1) 7:4 ALCHLD ...
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Pre-Production REGISTER ADDRESS Table 18 ALC Control Registers WHEN THE ALC IS DISABLED, THE INPUT PGA REMAINS AT THE LAST CONTROLLED VALUE OF THE ALC. AN INPUT GAIN UPDATE MUST BE MADE BY WRITING TO THE INPPGAVOLL/R REGISTER BITS. NORMAL ...
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WM8980 LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is ...
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Pre-Production ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when the gain is reducing. The decay time is the time constant used when ...
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WM8980 LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 20 ALC ...
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Pre-Production MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...
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WM8980 ALCMIN 000 001 010 011 100 101 110 111 Table 23 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing ...
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Pre-Production Figure 20 ALCLVL w WM8980 PP, Rev 3.8, May 2012 43 ...
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WM8980 Figure 21 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 25 ALC Hold Time Values w t (s) HOLD 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s Pre-Production ...
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Pre-Production PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...
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WM8980 The diagrams below show the response of the system to the same signal with and without noise gate. Figure 22 ALC Operation Above Noise Gate Threshold w Pre-Production PP, Rev 3.8, May 2012 46 ...
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Pre-Production Figure 23 Noise Gate Operation OUTPUT SIGNAL PATH The WM8980 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are ...
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WM8980 Figure 24 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker (LOUT2/ROUT2) ...
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Pre-Production The DAC output phase defaults to non-inverted. Setting DACPOLL will invert the DAC output phase on the left channel and DACPOLR inverts the phase on the right channel. AUTO-MUTE The DAC has an auto-mute function which applies an analogue ...
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WM8980 Figure 25 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 25, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. Signals ...
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Pre-Production REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 w BIT LABEL DEFAULT 3:0 LIMATK 0010 Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale proportionally with sample ...
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WM8980 REGISTER ADDRESS Table 30 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. ...
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Pre-Production REGISTER ADDRESS R20 EQ Band 3 Control Table 34 EQ Band 3 Control REGISTER ADDRESS R21 EQ Band 4 Control Table 35 EQ Band 4 Control REGISTER ADDRESS R22 EQ Band 5 Gain Control Table 36 EQ Band 5 ...
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WM8980 3D STEREO ENHANCEMENT The WM8980 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from ...
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Pre-Production Figure 26 Left/Right Output Channel Mixers w WM8980 PP, Rev 3.8, May 2012 55 ...
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WM8980 REGISTER ADDRESS R49 Output mixer control R50 Left channel output mixer control w BIT LABEL DEFAULT 5 DACR2LMIX 0 6 DACL2RMIX 0 0 DACL2LMIX 1 1 BYPL2LMIX 0 4:2 BYPLMIXVOL 000 5 AUXL2LMIX 0 8:6 AUXLMIXVOL 000 Pre-Production DESCRIPTION ...
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Pre-Production REGISTER ADDRESS R51 Right channel output mixer control R3 Power management 3 Table 39 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs, LOUT1 and ROUT1 can drive a 16 or 32 headphone load, ...
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WM8980 Figure 27 Headphone Outputs LOUT1 and ROUT1 REGISTER ADDRESS R52 LOUT1 Volume control R53 ROUT1 Volume control Table 40 OUT1 Volume Control w BIT LABEL DEFAULT 7 LOUT1ZC 0 6 LOUT1MUTE 0 5:0 LOUT1VOL 111001 8 HPVU Not latched ...
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Pre-Production Headphone Output using DC Blocking Capacitors: Figure 28 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f response. Smaller capacitance values will diminish the ...
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WM8980 Figure 29 Speaker Outputs LOUT2 and ROUT2 w Pre-Production PP, Rev 3.8, May 2012 60 ...
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Pre-Production REGISTER ADDRESS R54 LOUT2 (SPK) Volume control R55 ROUT2 (SPK) Volume control Table 41 Speaker Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the Bypass ...
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WM8980 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 42 Speaker Boost Stage Control SPKBOOST 0 1 Table 43 Output Boost Stage Details REGISTER ADDRESS R43 Beep control Table 44 AUXR – ROUT2 BEEP Mixer Function w BIT ...
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Pre-Production ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. ...
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WM8980 OUT3 can provide a buffered midrail headphone pseudo-ground left line output. OUT4 can provide a buffered midrail headphone pseudo-ground, a right line output mono mix output. REGISTER ADDRESS R56 OUT3 mixer control R57 OUT4 mixer ...
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Pre-Production Figure 33 Outputs OUT3 and OUT4 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 47 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST 0 1 Table 48 OUT3/OUT4 Output Boost Stage Details w BIT LABEL DEFAULT 3 ...
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WM8980 OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: 1. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal ...
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Pre-Production Table 49 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here (Mixer ...
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WM8980 ENABLING THE OUTPUTS Each analogue output of the WM8980 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the ...
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Pre-Production REGISTER ADDRESS R49 Table 52 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 35. This buffer can be enabled using the BUFIOEN register bit. If the ...
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WM8980 L/ROUT2EN/ OUT3/4EN Table 53 Unused Output Pin Tie-off Options VIDEO BUFFER DESCRIPTION The WM8980 incorporates a current mode output video buffer capable of operating from a 2.5V supply, with an input 3 programmed ...
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Pre-Production -10 -15 -20 -25 10 VIDEO BUFFER REGISTERS Video buffer enable / disable and gain are controlled via the following registers: REGISTER ADDRESS R3 Power management 3 R40 Video Buffer Table 54 Video Buffer Registers ...
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WM8980 TEST WAVEFORMS Figure 37 Black Needle Pulse (Full frame of white with a vertical black line) Figure 39 Multiburst (A horizontal multiburst of signals with frequencies ranging from 0.5MHz to 5.75MHz) CURRENT MODE OUTPUT The current mode output employed ...
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Pre-Production Figure 41 Video Buffer with 0dB Gain Figure 42 Video Buffer with 6dB Gain The outputs VBREF and VBOUT are current mirrored transistors with a 5:1 ratio, so that VBOUT VBREF A reference resistor ...
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WM8980 DIGITAL AUDIO INTERFACES The audio interface has four pins: ADCDAT: ADC data output DACDAT: DAC data input LRC: Data Left/Right alignment clock BCLK: Bit clock, for synchronisation The clock signals BCLK, and LRC can be ...
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Pre-Production In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be ...
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WM8980 In DSP/PCM mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency ...
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Pre-Production REGISTER ADDRESS R4 Audio Interface Control Table 55 Audio Interface Control ADCLRSWAP bit controls whether the ADC data appears in the right or left phase of the LRC clock as defined for each audio format. Similarly, DACLRSWAP can be ...
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WM8980 REGISTER ADDRESS R6 Clock Generation Control Table 56 Clock Control The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from MCLK (CLKSEL=0). When the internal clock is switched from one source to ...
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Pre-Production AUDIO SAMPLE RATES The WM8980 sample rates for the ADCs and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume ...
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WM8980 Figure 48 PLL and Clock Select Circuit The PLL frequency ratio PLLN = int R PLLK = int (2 Note: The PLL is designed to operate with best performance (shortest lock time and optimum stability) when ...
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Pre-Production The PLL performs best when f are shown in Table 60. MCLK DESIRED F2 OUTPUT (MHZ) (MHZ) (MHZ) (F1) 12 11.29 90.3168 12 12.288 98.304 13 11.29 90.3168 13 12.288 98.304 14.4 11.29 90.3168 14.4 12.288 98.304 19.2 11.29 ...
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WM8980 REGISTER ADDRESS R5 Companding Control Table 61 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) ...
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Pre-Production 120 100 Figure 49 u-Law Companding 120 100 Figure 50 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT The WM8980 has three dual purpose input/output pins and one dedicated GPIO. ...
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WM8980 When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection, depending on how the MODE pin is set. If setup as an input, the GPIO4 pin can also be used for ...
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Pre-Production Note that the GPIOPOL bits are not relevant for jack detection the signal detected at the pin which is used. The switching on/off of the outputs is fully configurable by the user. Each output, OUT1, OUT2, OUT3 ...
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WM8980 CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the wire mode as shown in Table 65. The ...
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Pre-Production In 2-wire mode the WM8980 has a fixed device address, 0011010. RESETTING THE CHIP The WM8980 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register ...
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WM8980 3. Enable unused output chosen from L/ROUT2, OUT3 or OUT4. If unused output not available, chose one of these outputs not required at power up. 4. Set BUFDCOPEN = 1 and BUFIOEN = 1 in register R1. 5. Set ...
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Pre-Production Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp towards ...
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WM8980 Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t capacitor ...
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Pre-Production SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off t dacint DAC Group Delay Table 67 Typical POR Operation (typical values, not tested) Notes: 1. The lineout charge time dependent upon the value of VMID decoupling capacitor ...
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WM8980 POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x ...
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Pre-Production REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX 0 00 Software Reset Power manage’t 1 BUFDCOP OUT4MIX Power manage’t 2 ROUT1EN LOUT1EN Power manage’t 3 OUT4EN OUT3EN Audio Interface BCP 4 ...
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WM8980 44 2C Input ctrl MBVSEL 45 2D Left INP PGA gain INPPGA INPPGAZC ctrl UPDATE Right INP PGA gain INPGA INPPGAZC 46 2E ctrl UPDATE Left ADC Boost ctrl PGABOOSTL 47 2F Right ADC Boost PGABOOSTR 48 30 ctrl ...
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Pre-Production REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER BIT LABEL ADDRESS 0 ...
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WM8980 REGISTER BIT LABEL ADDRESS 2 INPPGAENL 0 1 ADCENR 0 0 ADCENL 0 3 (03h) 8 OUT4EN 0 7 OUT3EN 0 6 LOUT2EN 0 5 ROUT2EN 0 4 VBUFEN 0 3 RMIXEN 0 2 LMIXEN 0 1 DACENR 0 ...
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Pre-Production REGISTER BIT LABEL ADDRESS 4 (04h) 8 BCP 0 7 LRP 0 6 4:3 FMT 10 2 DACLRSWAP 0 1 ADCLRSWAP 0 0 MONO 0 5 (05h) 8:6 000 5 WL8 0 4:3 DAC_COMP 00 2:1 ADC_COMP ...
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WM8980 REGISTER BIT LABEL ADDRESS 6 (06h) 8 CLKSEL 1 7:5 MCLKDIV 010 4:2 BCLKDIV 000 (07h) 8:4 00000 3:1 SR 000 0 SLOWCLKEN 0 8 (08h) 8:6 000 5:4 OPCLKDIV 00 3 GPIO1POL ...
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Pre-Production REGISTER BIT LABEL ADDRESS 2:0 GPIO1SEL 000 [2:0] 9 (09h) 8:7 JD_VMID 00 6 JD_EN 0 5:4 JD_SEL 00 3 GPIO4POL 0 2:0 GPIO4SEL 000 [2:0] 10 (0Ah) 8 SOFTMUTE 0 5 DACOSR128 0 2 ...
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WM8980 REGISTER BIT LABEL ADDRESS 11 (0Bh) 8 DACVU N/A 7:0 DACVOLL 11111111 12 (0Ch) 8 DACVU N/A 7:0 DACVOLR 11111111 13 (0Dh 7:4 JD_EN1 0000 3:0 JD_EN0 0000 14 (0Eh) 8 HPFEN 1 7 HPFAPP 0 6:4 ...
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Pre-Production REGISTER BIT LABEL ADDRESS 15 (0Fh) 8 ADCVU N/A 7:0 ADCVOLL 11111111 16 (10h) 8 ADCVU N/A 7:0 ADCVOLR 11111111 18 (12h) 8 EQ3DMODE 6:5 EQ1C 4:0 EQ1G 01100 19 (13h) 8 EQ2BW ...
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WM8980 REGISTER BIT LABEL ADDRESS 4:0 EQ3G 01100 21 (15h) 8 EQ4BW 6:5 EQ4C 01 4:0 EQ4G 01100 22 (16h) 8:7 0 6:5 EQ5C 01 4:0 EQ5G 01100 24 (18h) 8 LIMEN 0 7:4 LIMDCY 0011 w ...
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Pre-Production REGISTER BIT LABEL ADDRESS 3:0 LIMATK 0010 25 (19h) 8:7 00 6:4 LIMLVL 000 3:0 LIMBOOST 0000 27 (1Bh) 8 NFU 0 7 NFEN 0 6:0 NFA0[13:7] 0000000 28 (1Ch) 8 NFU 6:0 NFA0[6:0] 0000000 w ...
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WM8980 REGISTER BIT LABEL ADDRESS 29 (1Dh) 8 NFU 6:0 NFA1[13:7] 0000000 30 (1Eh) 8 NFU 6:0 NFA1[6:0] 0000000 32 (20h) 8:7 ALCSEL 5:3 ALCMAXGAIN 111 2:0 ALCMINGAIN 000 33 (21h) ...
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Pre-Production REGISTER BIT LABEL ADDRESS 3:0 ALCLVL 1011 34 (22h) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] 0011 3:0 ALCATK 0010 0010 35 (23h) 8:4 00000 w DEFAULT DESCRIPTION ALC target – sets signal level at ADC input 1111 : ...
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WM8980 REGISTER BIT LABEL ADDRESS 3 NGEN 0 2:0 NGTH 000 36 (24h) 8:5 0000 4 PLL 0 PRESCALE 3:0 PLLN[3:0] 1000 37 (25h) 8:6 000 5:0 PLLK[23:18] 01100 38 (26h) 8:0 PLLK[17:9] 010010011 39 (27h) 8:0 PLLK[8:0] 011101001 40 ...
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Pre-Production REGISTER BIT LABEL ADDRESS 3:1 BEEPVOL 000 0 BEEPEN 0 44 (2Ch) 8 MBVSEL R2_2INP 0 PGA 5 RIN2INP 1 PGA 4 RIP2INP 1 PGA L2_2INP 0 PGA 1 LIN2INP 1 PGA ...
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WM8980 REGISTER BIT LABEL ADDRESS 5:0 INPPGA 010000 VOLL 46 (2Eh) 8 INPPGA N/A UPDATE 7 INPPGA 0 ZCR 6 INPPGA 0 MUTER 5:0 INPPGA 010000 VOLR 47 (2Fh) 8 PGA 1 BOOSTL 7 0 6:4 L2_2 000 BOOSTVOL 3 ...
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Pre-Production REGISTER BIT LABEL ADDRESS 6:4 R2_2 000 BOOSTVOL 3 0 2:0 AUXR2 000 BOOSTVOL 49 (31h) 8 DACL2RMIX 0 5 DACR2LMIX 0 4 OUT4 0 BOOST 3 OUT3 0 BOOST 2 SPKBOOST 0 1 TSDEN 1 0 ...
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WM8980 REGISTER BIT LABEL ADDRESS 4:2 BYPLMIX 000 VOL 1 BYPL2L 0 MIX 0 DACL2L 1 MIX 51 (33h) 8:6 AUXRMIX 000 VOL 5 AUXR2R 0 MIX 4:2 BYPRMIX 000 VOL 1 BYPR2R 0 MIX 0 DACR2R 1 MIX 52 ...
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Pre-Production REGISTER BIT LABEL ADDRESS 5:0 LOUT1VOL 111001 53 (35h) 8 HPVU N/A 7 ROUT1ZC 6 ROUT1 0 MUTE 5:0 ROUT1VOL 111001 54 (36h) 8 SPKVU N/A 7 LOUT2ZC 6 LOUT2 0 MUTE 5:0 LOUT2VOL 111001 55 (37h) 8 SPKVU ...
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WM8980 REGISTER BIT LABEL ADDRESS 3 OUT4_2OUT3 0 2 BYPL2OUT3 0 1 LMIX2OUT3 0 0 LDAC2OUT3 1 57 (39h) 8 OUT4MUTE 0 5 HALFSIG 0 4 LMIX2OUT4 0 3 LDAC2OUT4 0 2 BYPR2OUT4 0 1 RMIX2OUT4 0 0 ...
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Pre-Production DIGITAL FILTER CHARACTERISTICS PARAMETER TEST CONDITIONS ADC Filter Passband +/- 0.025dB Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband +/- 0.035dB Passband Ripple Stopband Stopband Attenuation Group Delay ...
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WM8980 DAC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 1.5 Frequency (fs) Figure 55 DAC Digital Filter Frequency Response (128xOSR -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 ...
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Pre-Production HIGHPASS FILTER The WM8980 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter applications mode the filter ...
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WM8980 5-BAND EQUALISER The WM8980 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 65 to Figure 78 show the frequency responses of each filter with a sampling ...
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Pre-Production -10 - Frequency (Hz) Figure 70 EQ Band 3 – Peak Filter Centre Frequencies, EQ3B Figure -10 -15 ...
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WM8980 -10 - Frequency (Hz) Figure 73 EQ Band 4 – Peak Filter Centre Frequencies, EQ3B Figure -10 -15 ...
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Pre-Production Figure 78 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with ...
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WM8980 APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 79 Recommended External Component Diagram w Pre-Production PP, Rev 3.8, May 2012 120 ...
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Pre-Production PACKAGE DIAGRAM FL: 40 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 SIDE VIEW C SEATING PLANE Exposed lead Half ...
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... Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. ...
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... Pre-Production REVISION HISTORY DATE REV ORIGINATOR 01/11/11 3.8 JMacD 01/11/11 3.8 JMacD 05/01/12 3 CHANGES Order codes changed from WM8980GEFL/R and WM8980GEFL/RV to WM8980CGEFL/V and WM8980CGEFL/RV to reflect change to copper wire bonding. Package Diagram changed to DM105.A. Corrected GPIO4SEL description. WM8980 PP, Rev 3.8, May 2012 123 ...