WM8985_07 WOLFSON [Wolfson Microelectronics plc], WM8985_07 Datasheet
WM8985_07
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WM8985_07 Summary of contents
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Multimedia CODEC With Class D Headphone and Line Out DESCRIPTION The WM8985 is a low power, high quality, feature-rich stereo codec designed for portable multimedia applications that require low power consumption and high quality audio. The device integrates preamps ...
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WM8985 BLOCK DIAGRAM w Pre-Production PP, Rev 3.5, March 2007 2 ...
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Pre-Production DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................2 PIN CONFIGURATION...........................................................................................5 ORDERING INFORMATION ..................................................................................5 PIN DESCRIPTION ................................................................................................6 ABSOLUTE MAXIMUM RATINGS.........................................................................7 RECOMMENDED OPERATING CONDITIONS .....................................................7 ELECTRICAL CHARACTERISTICS ......................................................................8 TERMINOLOGY .......................................................................................................... 14 AUDIO PATHS OVERVIEW .................................................................................16 SIGNAL TIMING REQUIREMENTS .....................................................................17 SYSTEM CLOCK ...
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WM8985 APPLICATIONS INFORMATION .......................................................................116 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 116 PACKAGE DIAGRAM ........................................................................................117 ADDRESS: ................................................................................................................ 118 w Pre-Production PP, Rev 3.5, March 2007 4 ...
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Pre-Production PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8985GEFL -25°C to +85°C WM8985GEFL/R -25°C to +85°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN ( mm) (Pb-free) 32-lead QFN ( mm) ...
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WM8985 PIN DESCRIPTION PIN NAME 1 LIP Analogue input Analogue input 2 LIN 3 L2/GPIO2 Analogue input 4 RIP Analogue input 5 RIN Analogue input 6 R2/GPIO3 Analogue input 7 LRC Digital Input / Output 8 BCLK Digital Input / ...
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Pre-Production ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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WM8985 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Microphone Input PGA Inputs (LIP, LIN, RIP, RIN, L2, R2) INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale Input Signal Level – 1 Single-ended input via LIN/RIN Full-scale Input Signal Level ...
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Pre-Production Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Auxiliary Analogue Inputs (AUXL, AUXR) 2 Full-scale Input Signal Level Input Resistance Input Capacitance Gain range from AUXL and AUXR input to left and right input PGA mixers AUXLBOOSTVOL and AUXRBOOSTVOL step size ...
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WM8985 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER L2_2BOOSTVOL, R2_2BOOSTVOL, ADCLVOL and ADCRVOL = 0dB 3 Signal to Noise Ratio 4 Total Harmonic Distortion 5 Total Harmonic Distortion + Noise 6 Channel Separation DAC to left and right mixers into 10kΩ ...
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Pre-Production Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER DAC to L/R mixer into 10kΩ / 50pF load on L/ROUT2, class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB 1 Full-scale output 3 Signal to Noise Ratio 4 Total Harmonic Distortion ...
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WM8985 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER DAC to left and right mixer into headphone 16Ω load on LOUT2 and ROUT2, Class AB mode LOUT2VOL, ROUT2VOL, DACLVOL and DACRVOL = 0dB Full-scale output 3 Signal to Noise Ratio 4 Total ...
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Pre-Production Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER LIN and RIN input PGA to input boost stage into 10kΩ / 50pF load on OUT3/OUT4 outputs INPPGAVOLL, INPPGAVOLR, PGABOOSTL and PGABOOSTR = 0dB Full-scale output voltage, 0dB gain 3 Signal to Noise ...
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WM8985 Test Conditions DCVDD=1.8V, AVDD1=AVDD2=DBVDD=3.3V, T PARAMETER Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level Input Capacitance Input leakage TERMINOLOGY 1. Full-scale input and output levels scale in relation to AVDD or ...
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Pre-Production POWER CONSUMPTION Typical power consumption for various scenarios is shown below. All measurements are made with quiescent signal. Description Off (Default Settings) Standby mode (Lowest Power) DAC Playback 32Ω load L/ROUT2 - Class AB Mode fs=44.1kHz ADC Stereo Line ...
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WM8985 AUDIO PATHS OVERVIEW Figure 1 Audio Paths Overview w Pre-Production PP, Rev 3.5, March 2007 16 ...
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Pre-Production SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 2 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, DGND=AGND1=AGND2=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note: 1. PLL pre-scaling and PLL N and K ...
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WM8985 Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold ...
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Pre-Production CONTROL INTERFACE TIMING – 3-WIRE MODE 3-wire mode is selected by connecting the MODE pin high. Figure 5 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD1 = AVDD2 = 3.3V, DGND ...
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WM8985 CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK Figure 6 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD1=AVDD2=3.3V, MCLK = 256fs, 24-bit data, unless otherwise ...
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Pre-Production INTERNAL POWER ON RESET CIRCUIT Figure 7 Internal Power on Reset Circuit Schematic The WM8985 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used to reset the digital logic into a default state after power ...
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WM8985 Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1 Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that DCVDD is already up to specified operating voltage. When AVDD1 ...
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Pre-Production RECOMMENDED POWER UP/DOWN SEQUENCE In order to minimise output pop and click noise recommended that the WM8985 device is powered up and down under control using the following sequences: Power Up ...
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WM8985 Figure 10 ADC Power Up and Down Sequence (not to scale) SYMBOL t midrail_on t midrail_off t adcint ADC Group Delay Table 3 Typical POR Operation (Typical Simulated Values) w MIN TYPICAL MAX UNIT 300 ms >6 s 2/fs ...
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Pre-Production Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD1 power supply rise time. 2. The analogue input pin discharge time, t capacitor ...
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WM8985 SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off t dacint DAC Group Delay Table 4 Typical POR Operation (Typical Simulated Values) Notes: 1. The lineout charge time, t dependent upon the value of VMID decoupling capacitor and VMID ...
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Pre-Production DEVICE DESCRIPTION INTRODUCTION The WM8985 is a low power audio codec combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. FEATURES The chip offers great flexibility in use, and so ...
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WM8985 OUT3 and OUT4 can be configured to provide an additional stereo or mono differential lineout from the output of the DACs, the mixers or the input microphone boost stages. They can also provide a midrail reference for pseudo differential ...
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Pre-Production and the non-inverting input of the input PGA clamped to VMID. Figure 12 Microphone Input PGA Circuit The input PGAs are enabled by the INPPGAENL and INPPGAENR register bits. REGISTER ADDRESS R2 (02h) Power Management 2 Table 5 Input ...
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WM8985 REGISTER ADDRESS R44 (2Ch) Input Control Table 6 Input PGA Control INPUT PGA VOLUME CONTROLS The input microphone PGAs have a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the LIN/RIN input to the PGA ...
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Pre-Production REGISTER ADDRESS R45 (20h) Left channel input PGA volume control R46 (2Eh) Right channel input PGA volume control R32 (20h) ALC control 1 Table 7 Input PGA Volume Control w BIT LABEL DEFAULT 5:0 INPPGAVOLL 010000 (0dB) 6 INPPGAMUTEL ...
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WM8985 VOLUME UPDATES Volume settings will not be applied to the PGAs until a '1' is written to one of the INPPGAVU bits. This is to allow left and right channels to be updated at the same time, as shown ...
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Pre-Production Figure 15 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8985 will automatically update the volume. The volume updates will occur between one and two timeout ...
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WM8985 AUXILLIARY INPUTS There are two auxiliary inputs, AUXL and AUXR which can be used for a variety of purposes such as stereo line inputs ‘beep’ input signal to be mixed with the outputs. The AUXL/R inputs ...
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Pre-Production The input PGA paths can have a +20dB boost (PGABOOSTL/R=1), a 0dB pass through (PGABOOSTL/R= completely isolated from the input boost circuit (INPPGAMUTEL/R=1). REGISTER ADDRESS R47 (2Fh) Left Input BOOST control R48 (30h) Right Input BOOST control ...
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WM8985 REGISTER ADDRESS R42 (2Ah) OUT4 to ADC R47 (2Fh) Left channel Input BOOST control R48 (30h) Right channel Input BOOST control w BIT LABEL DEFAULT 8:6 OUT4_2ADCVOL 000 5 OUT4_2LNR 0 2:0 AUXL2BOOSTVOL 000 6:4 L2_2BOOSTVOL 000 2:0 AUXR2BOOSTVOL ...
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Pre-Production REGISTER ADDRESS Table 9 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 (02h) Power management 2 Table 10 Input BOOST Enable Control MICROPHONE BIASING CIRCUIT The MICBIAS output ...
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WM8985 Figure 18 Microphone Bias Schematic ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8985 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full ...
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Pre-Production The polarity of the output signal can also be changed under software control using the ADCLPOL/ADCRPOL register bit. ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate ...
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WM8985 PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these ...
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Pre-Production NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth 1000 100 48000 Hz = π w ...
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WM8985 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8985 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...
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Pre-Production REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (13ms/6dB) 0011 (2.9ms/6dB) 3:0 ALCATK 0010 [3:0] (832us/6dB) 0010 (182us/6dB) WM8985 DESCRIPTION 0000 = -22.5dBFS ALC ...
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WM8985 REGISTER ADDRESS Table 20 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL ...
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Pre-Production LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC is ...
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WM8985 NORMAL MODE ALCMODE = 0 (Normal Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 0 (Normal Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 19 ALC ...
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Pre-Production LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 20 ALC ...
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WM8985 MINIMUM AND MAXIMUM GAIN The ALCMIN and ALCMAX register bits set the minimum/maximum gain value that the PGA can be set to whilst under the control of the ALC. This has no effect on the PGA when ALC is ...
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Pre-Production ALCMIN 000 001 010 011 100 101 110 111 Table 25 ALC Min Gain Values Note that if the ALC gain setting strays outside the ALC operating range, either by starting the ALC outside of the range or changing ...
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WM8985 Figure 24 ALCLVL w Pre-Production PP, Rev 3.5, March 2007 50 ...
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Pre-Production Figure 25 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 27 ALC Hold Time Values w t (s) HOLD 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s WM8985 ...
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WM8985 PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped ...
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Pre-Production Figure 21 ALC Operation Above Noise Gate Threshold w WM8985 PP, Rev 3.5, January 2007 53 ...
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WM8985 Figure 22 Noise Gate Operation OUTPUT SIGNAL PATH The WM8985 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC are enabled ...
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Pre-Production Figure 23 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1, LOUT2/ROUT2) or ...
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WM8985 The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters the multi-bit, sigma-delta DACs, which convert high quality analogue audio signal. The multi-bit DAC ...
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Pre-Production Figure 24 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 24, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. LIMATK ...
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WM8985 REGISTER ADDRESS R24 (18h) DAC digital limiter control 1 R25 (19h) DAC digital limiter control 2 w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 Pre-Production DESCRIPTION Limiter Attack time (per 6dB ...
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Pre-Production REGISTER ADDRESS Table 24 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ...
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WM8985 REGISTER ADDRESS R20 (14h) EQ Band 3 Control Table 28 EQ Band 3 Control REGISTER ADDRESS R21 (15h) EQ Band 4 Control Table 29 EQ Band 4 Control REGISTER ADDRESS R22 (16h) EQ Band 5 Gain Control Table 30 ...
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Pre-Production 3D STEREO ENHANCEMENT The WM8985 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from ...
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WM8985 LEFT AND RIGHT OUTPUT CHANNEL MIXERS The left and right output channel mixers are shown in Figure 25. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. ...
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Pre-Production REGISTER ADDRESS R43 (2Bh) Output mixer control R43 (2Bh) Output mixer control R49 (31h) Output mixer control R50 (32h) Left channel output mixer control w BIT LABEL DEFAULT 8 BYPL2RMIX 0 7 BYPR2LMIX 0 5 DACR2LMIX 0 6 DACL2RMIX ...
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WM8985 R51 (33h) Right channel output mixer control R3 (03h) Power management 3 Table 33 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, ...
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Pre-Production Headphone Output using DC Blocking Capacitors DC Coupled Headphone Output Figure 26 Recommended Headphone Output Configurations When DC blocking capacitors are used, their capacitance and the load resistance together determine the lower cut-off frequency of the output signal, f ...
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WM8985 REGISTER ADDRESS R52 (34h) LOUT1 Volume control R53 ROUT1 Volume control Table 34 OUT1 Volume Control w BIT LABEL DEFAULT 5:0 LOUT1VOL 111001 (0dB) 6 LOUT1MUTE 0 7 LOUT1ZC 0 8 HPVU Not latched 5:0 ROUT1VOL 111001 (0dB) 6 ...
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Pre-Production CLASS D / CLASS AB HEADPHONE OUTPUTS (LOUT2 AND ROUT2) The outputs LOUT2 and ROUT2 are designed to drive two headphone loads of 16Ω or 32Ω or line outputs (See Headphone Output and Line Output sections, respectively). Each output ...
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WM8985 Figure 28 LOUT2 and ROUT2 Class AB Headphone Configuration The output configurations shown in figures 29 and 30 are both suitable for class AB operation. The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be ...
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Pre-Production REGISTER ADDRESS R54 (36h) LOUT2 Volume control R55 (37h) ROUT2 Volume control Table 36 OUT2 Volume Control ZERO CROSS TIMEOUT A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs ...
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WM8985 OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins provide an additional stereo line output, a mono output differential output. There is a dedicated analogue mixer for OUT3 and one for OUT4 as shown in Figure 29. The ...
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Pre-Production REGISTER ADDRESS R56 (38h) OUT3 mixer control R57 (39h) OUT4 mixer control Table 38 OUT3/OUT4 Mixer Registers w BIT LABEL DEFAULT 6 OUT3MUTE 0 3 OUT4_2OUT3 0 2 BYPL2OUT3 0 1 LMIX2OUT3 0 0 LDAC2OUT3 1 7 OUT3_2OUT4 0 ...
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WM8985 ENABLING THE OUTPUTS Each analogue output of the WM8985 can be independently enabled or disabled. The analogue mixer associated with each output has a separate enable bit. All outputs are disabled by default. To save power, unused parts of ...
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Pre-Production REGISTER ADDRESS R49 (31h) Table 41 Disabled Outputs to VREF Resistance A dedicated buffer is available for biasing unused analogue I/O pins as shown in Figure 30. This buffer can be enabled using the BUFIOEN register bit. Figure 30 ...
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WM8985 DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and LRC can be outputs when the WM8985 operates as a master, or inputs when slave (see Master and ...
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Pre-Production Figure 32 Right Justified Audio Interface (assuming n-bit word length mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then ...
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WM8985 Figure 35 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) Figure 36 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave) Figure 37 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Pre-Production PP, Rev 3.5, March 2007 76 ...
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Pre-Production REGISTER ADDRESS R4 (04h) Audio Interface Control R5 Table 43 Audio Interface Control Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the device will operate in 24-bit mode. AUDIO ...
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WM8985 REGISTER ADDRESS R6 (06h) Clock Generation Control Table 44 Clock Control AUDIO SAMPLE RATES The WM8985 ADC high pass filter, ALC and DAC limiter characteristics are sample rate dependent. SR should be set to the correct sample rate or ...
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Pre-Production MASTER CLOCK AND PHASE LOCKED LOOP (PLL) The WM8985 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8985 audio functions from another external clock, e.g. in telecoms applications. Generate and ...
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WM8985 REGISTER ADDRESS R36 (24h) PLL N value R37 (25h) PLL K value 1 R38 (26h) PLL K Value 2 R39 (27h) PLL K Value 3 Table 47 PLL Frequency Ratio Control The PLL performs best when f are shown ...
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Pre-Production LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from the ADC audio interface is fed directly into the DAC data input. COMPANDING The WM8985 supports A-law and µ-law companding on ...
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WM8985 120 100 Figure 39 µ-Law Companding 120 100 Figure 40 A-Law Companding w u-law Companding 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0 0 0.2 0.4 Normalised Input ...
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Pre-Production GENERAL PURPOSE INPUT/OUTPUT The WM8985 has three dual purpose input/output pins. • • • The GPIO2 and GPIO3 functions are provided for use as jack detection inputs. The GPIO1 function is provided for use as jack detection input or ...
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WM8985 For further details of the jack detect operation see the OUTPUT SWITCHING section. OUTPUT SWITCHING (JACK DETECT) When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch control input to automatically ...
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Pre-Production REGISTER ADDRESS R9 (09h) GPIO control R13 (00h) Table 46 Jack Detect Register Control Bits CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire control interface. The ...
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WM8985 2-WIRE SERIAL CONTROL MODE The WM8985 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the ...
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Pre-Production POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR128 and DACOSR128 the oversampling rate may be doubled. 64x ...
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WM8985 VMID The analogue circuitry will not operate unless VMID is enabled. The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the start-up time of the VMID circuit. REGISTER ADDRESS R1 ...
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Pre-Production REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX 0 00 Software Reset 01 1 Power manage’ Power manage’t 2 ROUT1EN 3 03 Power manage’t 3 OUT4EN 4 04 Audio Interface BCP 5 05 Companding ...
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WM8985 REGISTER B8 ADDR NAME B[15:9] DEC HEX 44 2C Input ctrl MBVSEL 45 2D Left INP PGA gain INPGAVU ctrl 46 2E Right INP PGA gain INPGAVU ctrl 47 2F Left ADC Boost ctrl PGA BOOSTL 48 30 Right ...
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Pre-Production REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER BIT LABEL ADDRESS 0 ...
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WM8985 REGISTER BIT LABEL ADDRESS 1 ADCENR 0 ADCENL 3 (03h) 8 OUT4EN 7 OUT3EN 6 ROUT2EN 5 LOUT2EN 4 3 RMIXEN 2 LMIXEN 1 DACENR 0 DACENL 4 (04h) 8 BCP 7 LRP 6:5 WL 4:3 FMT w DEFAULT ...
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Pre-Production REGISTER BIT LABEL ADDRESS 2 DLRSWAP 1 ALRSWAP 0 MONO 5 (05h) 8:6 5 WL8 4:3 DAC_COMP 2:1 ADC_COMP 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV w DEFAULT DESCRIPTION 0 Controls whether DAC data appears in ‘right’ or ...
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WM8985 REGISTER BIT LABEL ADDRESS 4:2 BCLKDIV (07h) 8 M128ENB 7:4 DCLKDIV 3 SLOWCLKEN 8 (08h) 8 GPIO1GP 7 GPIO1GPU 6 GPIO1GPD w DEFAULT DESCRIPTION 000 Configures the BCLK output frequency, for use when ...
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Pre-Production REGISTER BIT LABEL ADDRESS 5:4 OPCLKDIV 3 GPIO1POL 2:0 GPIO1SEL [2:0] 9 (09h) 8:7 6 JD_EN 5:4 JD_SEL 3:0 10 (0Ah) 8:7 6 SOFTMUTE 5:4 3 DACOSR128 2 AMUTE 1 DACPOLR 0 DACPOLL 11 (0Bh) 8 DACVU w DEFAULT ...
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WM8985 REGISTER BIT LABEL ADDRESS 7:0 DACVOLL 12 (0Ch) 8 DACVU 7:0 DACVOLR 13 (0Dh) 8 7:4 JD_EN1 3:0 JD_EN0 14 (0Eh) 8 HPFEN 7 HPFAPP 6:4 HPFCUT 3 ADCOSR 128 2 1 ADCRPOL 0 ADCLPOL 15 (0Fh) 8 ADCVU ...
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Pre-Production REGISTER BIT LABEL ADDRESS 7:0 ADCVOLL 16 (10h) 8 ADCVU 7:0 ADCVOLR 18 (12h) 8 EQ3DMODE 7 6:5 EQ1C 4:0 EQ1G 19 (13h) 8 EQ2BW 7 6:5 EQ2C 4:0 EQ2G 20 (14h) 8 EQ3BW 7 6:5 EQ3C 4:0 EQ3G ...
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WM8985 REGISTER BIT LABEL ADDRESS 6:5 EQ4C 4:0 EQ4G 22 (16h) 8:7 6:5 EQ5C 4:0 EQ5G 23 (17h) 8 CLASSDEN 7:0 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK w DEFAULT DESCRIPTION 01 EQ Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz ...
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Pre-Production REGISTER BIT LABEL ADDRESS 25 (19h) 8:7 6:4 LIMLVL 3:0 LIMBOOST 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 ...
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WM8985 REGISTER BIT LABEL ADDRESS 32 (20h) 8:7 ALCSEL 6 5:3 ALCMAXGAIN 2:0 ALCMINGAIN 33 (21h) 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY [3:0] w DEFAULT DESCRIPTION 00 ALC function select: 00=ALC off 01=ALC right only 10=ALC ...
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Pre-Production REGISTER BIT LABEL ADDRESS 3:0 ALCATK 35 (23h) 8:4 3 NGEN 2:0 NGTH 36 (24h) 8:5 4 PLLPRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] w DEFAULT DESCRIPTION Per step Per 6dB 0000 90.8us 726.4us ...
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WM8985 REGISTER BIT LABEL ADDRESS 39 (27h) 8:0 PLLK[8:0] 41 (29h) 8:4 3:0 DEPTH3D 42 (2Ah) 8:6 OUT4_2ADCVOL 5 OUT4_2LNR 4:0 2 POBCTRL 43 (2Bh) 8 BYPL2RMIX 7 BYPR2LMIX 6 5 MUTERPGA2INV 4 INVROUT2 3:1 BEEPVOL 0 BEEPEN 44 (2Ch) ...
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Pre-Production REGISTER BIT LABEL ADDRESS 5 RIN2INPPGA 4 RIP2INPPGA 3 2 L2_2INPPGA 1 LIN2INPPGA 0 LIP2INPPGA 45 (2Dh) 8 INPPGAU 7 INPPGAZCL 6 INPPGAMUTEL 5:0 INPPGAVOLL 46 (2Eh) 8 INPPGAU 7 INPPGAZCR 6 INPPGAMUTER w DEFAULT DESCRIPTION 1 Connect RIN ...
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WM8985 REGISTER BIT LABEL ADDRESS 5:0 INPPGAVOLR 47 (2Fh) 8 PGABOOSTL 7 6:4 L2_2BOOSTVOL 3 2:0 AUXL2BOOSTVOL 48 (30h) 8 PGABOOSTR 7 6:4 R2_2BOOSTVOL 3 2:0 AUXR2BOOSTVOL 49 (31h) 8:7 6 DACL2RMIX w DEFAULT DESCRIPTION 010000 Right channel input PGA ...
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Pre-Production REGISTER BIT LABEL ADDRESS 5 DACR2LMIX 4:3 2 TSOPCTRL 1 TSDEN 0 VROI 50 (32h) 8:6 AUXLMIXVOL 5 AUXL2LMIX 4:2 BYPLMIXVOL 1 BYPL2L MIX 0 DACL2L MIX 51 (33h) 8:6 AUXRMIXVOL 5 AUXR2RMIX w DEFAULT DESCRIPTION 0 Right DAC ...
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WM8985 REGISTER BIT LABEL ADDRESS 4:2 BYPRMIXVOL 1 BYPR2RMIX 0 DACR2RMIX 52 (34h) 8 OUT1VU 7 LOUT1ZC 6 LOUT1MUTE 5:0 LOUT1VOL 53 (35h) 8 OUT1VU 7 ROUT1ZC 6 ROUT1MUTE 5:0 ROUT1VOL 54 (36h) 8 OUT2VU 7 LOUT2ZC 6 LOUT2MUTE w ...
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Pre-Production REGISTER BIT LABEL ADDRESS 5:0 LOUT2VOL 55 (37h) 8 OUT2VU 7 ROUT2ZC 6 ROUT2MUTE 5:0 ROUT2VOL 56 (38h) 8:7 6 OUT3MUTE 5:4 3 OUT4_2OUT3 2 BYPL2OUT3 1 LMIX2OUT3 0 LDAC2OUT3 57 (39h OUT3_2OUT4 6 OUT4MUTE 5 HALFSIG ...
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WM8985 REGISTER BIT LABEL ADDRESS 2 BYPR2OUT4 1 RMIX2OUT4 0 RDAC2OUT4 61 (39h) 8 7:0 w DEFAULT DESCRIPTION 0 Right ADC input to OUT4 0 = disabled 1= enabled 0 Right DAC mixer to OUT4 0 = disabled 1= enabled ...
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Pre-Production DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 54 Digital Filter Characteristics TERMINOLOGY ...
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WM8985 DAC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 Frequency (fs) Figure 40 DAC Digital Filter Frequency Response (128xOSR -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 ...
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Pre-Production HIGHPASS FILTER The WM8985 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter 3.7Hz. frequency -10 -15 -20 ...
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WM8985 5-BAND EQUALISER The WM8985 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling ...
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Pre-Production -10 - Frequency (Hz) Figure 55 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure -10 - ...
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WM8985 -10 - Frequency (Hz) Figure 58 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW -10 - ...
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Pre-Production Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with ...
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WM8985 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 External Component Diagram 1. When operating LOUT2 and ROUT2 in class D mode recommended that LC filtering is placed as close to the LOUT2 and ROUT2 pins as possible. Low ...
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Pre-Production PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE 5 SEE DETAIL A CORNER D2 TIE BAR B D2 EXPOSED 6 GROUND PADDLE BOTTOM VIEW (A3) 1 SIDE VIEW ...
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... Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon ...