ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet
ISPPAC-CLK5510V
Available stocks
Related parts for ISPPAC-CLK5510V
ISPPAC-CLK5510V Summary of contents
Page 1
August 2004 Features ■ 10MHz to 320MHz Input/Output Operation ■ Low Output to Output Skew (<50ps) ■ Low Jitter Peak-to-Peak(<70ps) ■ Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, ...
Page 2
Lattice Semiconductor General Description and Overview The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides sin- gle-ended or five differential clock outputs, while ...
Page 3
Lattice Semiconductor Figure 2. ispClock5520 Functional Block Diagram PS0 PS1 Profile Select Control REFSEL REFA+ INPUT REFA- DIVIDER 0 M REFVTT (1-32) 1 REFB+ REFB- FEEDBACK N DIVIDER (1-32) JTAG INTERFACE TDI TMS LOCK RESET PLL_BYPASS ...
Page 4
Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage ...
Page 5
Lattice Semiconductor Performance Characteristics – Power Supply Symbol Parameter I Core Supply Current CCD I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1. Supply current consumed by each ...
Page 6
Lattice Semiconductor DC Electrical Characteristics – Differential LVPECL Symbol Parameter V Input Voltage High IH V Input Voltage Low Output High Voltage Output Low Voltage OL 1. 100Ω differential termination. DC Electrical Characteristics – ...
Page 7
Lattice Semiconductor Switching Characteristics – Timing Adders for I/O Modes Adder Type Base Parameter( Input Adders IOI LVTTL_in LVCMOS18_in LVCMOS25_in LVCMOS33_in SSTL2_in SSTL3_in HSTL_in LVDS_in LVPECL_in Output Adders IOO LVTTL_out LVCMOS18_out LVCMOS25_out LVCMOS33_out SSTL2_out SSTL3_out ...
Page 8
Lattice Semiconductor Output Test Loads Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load Figure ...
Page 9
Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance IN C Input Capacitance IN R Output Resistance OUT Conditions Rin=40Ω setting Rin=45Ω setting Rin=50Ω setting Rin=55Ω setting Rin=60Ω setting Rin=65Ω setting Rin=70Ω setting Rout≈20Ω setting, VCCO=1.5V ...
Page 10
Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference input frequency f REF range t Reference input clock HIGH and CLOCKHI, t LOW times CLOCKLO t RINP, Input rise and fall times t FINP M M-divider range DIV N N-Divider ...
Page 11
Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per range STEPS 2 t Skew Step Size SKSTEP t Skew Time Accuracy SKERR 1. ...
Page 12
Lattice Semiconductor Timing Specifications (Cont.) Boundary Scan Logic Symbol t TCK (BSCAN Test) Clock Cycle BTCP t TCK (BSCAN Test) Pulse Width High BTCH t TCK (BSCAN Test) Pulse Width Low BTCL t TCK (BSCAN Test) Setup Time BTSU t ...
Page 13
Lattice Semiconductor Timing Diagrams Figure 7. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH GKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 8. Programming Timing Diagram VIH ...
Page 14
Lattice Semiconductor Typical Performance Characteristics I vs. f CCD (Normalized to 640MHz) 1.2 1 0.8 0.6 0.4 0.2 0 300 400 500 f (MHz) VCO Typical Skew Error vs. Setting (Skew Mode = FINE, f 100 ...
Page 15
Lattice Semiconductor match. The option of which mode to use is programmable and may be set using PAC-Designer software (available from Lattice’s web site at www.latticesemi.com). In phase-lock mode the lock detector asserts the LOCK signal as soon as a ...
Page 16
Lattice Semiconductor The choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2 ...
Page 17
Lattice Semiconductor Table 3. Nominal Output Duty Cycle vs. V Divider Setting V DC PLL_BYPASS Mode The PLL_BYPASS mode is provided so that input ...
Page 18
Lattice Semiconductor Figure 12. ispClock5500 Clock Reference Input Structure (REFA+/- Pair Shown) ispClock5500 REFA+ REFA REFVTT The following usage guidelines are suggested for interfacing to supported logic families. LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be ...
Page 19
Lattice Semiconductor One important point to note is that the termination supplies must have low impedance and be able to both source and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive divider network, which ...
Page 20
Lattice Semiconductor LVDS/Differential LVPECL The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be engaged and set to 50Ω. The REFVTT pin, however, should be left unconnected. This creates a floating 100Ω ...
Page 21
Lattice Semiconductor Please note that while the above discussions specify using 50Ω termination impedances, the actual impedance required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The actual impedance required will be ...
Page 22
Lattice Semiconductor Each of the ispClock5500’s output driver banks can be configured to support the following logic outputs: • LVTTL • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • LVDS • Differential LVPECL (3.3V) To provide LVTTL, ...
Page 23
Lattice Semiconductor loads and to the ≈20Ω setting for driving HSTL. The far end of the transmission line must be terminated to an appropriate VTT voltage through a 50Ω resistor. Figure 20. Configuration for SSTL2, SSTL3, and HSTL Output Modes ...
Page 24
Lattice Semiconductor With a maximum recommended operating junction temperature (T maximum allowable ambient temperature ( AMAX where Θ °C/W in still air for the ispClock5520’s TQFP100 package. JA The above analysis represents the worst-case scenario. ...
Page 25
Lattice Semiconductor Figure 22b shows another derating curve, derived under the assumption that the output frequency is 100MHz. For many applications, 100MHz outputs will be a more realistic scenario. Comparing the maximum temperature limits of Figure 22b with Figure 22a, ...
Page 26
Lattice Semiconductor Table 6. SGATE Function SGATE Bank Controlled by SGATE Skew Control Units Each of the ispClock5500’s clock outputs is supported by a skew control unit which allows the user to insert an ...
Page 27
Lattice Semiconductor Figure 23. Additional Factor-of-2 Division in Coarse Mode VCO When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency will attempt to double to compensate for the additional divide-by-2 ...
Page 28
Lattice Semiconductor One can also program a user-defined skew between two outputs using the skew control units. Because the pro- grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is very accurate. ...
Page 29
Lattice Semiconductor • PLL Loop filter settings • Output Skew settings Input/Output logic configuration (logic family, I/O impedance, slew rate) is independent of the profile selected. When a profile is changed by changing the values of the PS0 and PS1 ...
Page 30
Lattice Semiconductor In-System Programming The ispClock5500 is an In-System Programmable (ISP™) device. This is accomplished by integrating all E configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once ...
Page 31
Lattice Semiconductor IEEE Standard 1149.1 Interface (JTAG) Serial Port Programming Interface Communication with the ispClock5500 is facilitated via an IEEE 1149.1 test access port (TAP used by the ispClock5500 both as a serial programming interface, and for boundary ...
Page 32
Lattice Semiconductor Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by ...
Page 33
Lattice Semiconductor facturer to determine. The instruction word length is not mandated other than minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- ...
Page 34
Lattice Semiconductor type and version code (Figure 30). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device issuing a Test-Logic-Reset instruction. The bit code for this instruction is ...
Page 35
Lattice Semiconductor VERIFY – This instruction loads data from the E shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR – This instruction copies the E umn register and then auto-increments the value ...
Page 36
Lattice Semiconductor Pin Descriptions Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘5’ VCC VCCO_6 Output Driver ...
Page 37
Lattice Semiconductor Pin Descriptions (Continued) Pin Name Description VCCD Digital Core VCC GNDD Digital GND VCCJ JTAG interface VCC REFA+ Clock Reference A positive input REFA- Clock Reference A negative input REFB+ Clock Reference B positive input REFB- Clock Reference ...
Page 38
Lattice Semiconductor VCCA, GNDA – These pins provide analog supply and ground for the ispClock5500 family’s internal analog cir- cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu- ...
Page 39
Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING ...
Page 40
Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL ...
Page 41
... Device Family Device Number CLK5510 CLK5520 Ordering Information Conventional Packaging Part Number ispPAC-CLK5510V-01T48C ispPAC-CLK5520V-01T100C Part Number ispPAC-CLK5510V-01T48I ispPAC-CLK5520V-01T100I Lead-Free Packaging Part Number ispPAC-CLK5510V-01TN48C ispPAC-CLK5520V-01TN100C Part Number ispPAC-CLK5510V-01TN48I ispPAC-CLK5520V-01TN100I Commercial Clock Outputs Supply Voltage 10 3.3V 20 3.3V Industrial Clock Outputs Supply Voltage 10 3.3V 20 3.3V Commercial ...
Page 42
... TQFP VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 ispClock5500 Family Data Sheet ispPAC CLK5510V-01T48C VCCJ TDO LOCK VCCD GNDO_4 BANK_4A BANK_4B VCCO_4 ...
Page 43
... VCCO_1 7 BANK_1B 8 BANK_1A 9 GNDO_1 10 VCCO_2 11 BANK_2B 12 BANK_2A 13 GNDO_2 14 VCCO_3 15 BANK_3B 16 BANK_3A 17 GNDO_3 18 VCCO_4 19 BANK_4B 20 BANK_4A 21 GNDO_4 22 n/c 23 n/c 24 n/c 25 ispPAC-CLK5520V-01T100C 43 ispClock5500 Family Data Sheet 75 n/c 74 VCCJ 73 TDO 72 LOCK 71 VCCD 70 GNDO_9 69 BANK_9A 68 BANK_9B 67 VCCO_9 66 GNDO_8 65 BANK_8A 64 BANK_8B 63 VCCO_8 62 GNDO_7 61 BANK_7A 60 BANK_7B 59 VCCO_7 58 GNDO_6 ...