GS1503BCVE2 GENNUM [Gennum Corporation], GS1503BCVE2 Datasheet
GS1503BCVE2
Related parts for GS1503BCVE2
GS1503BCVE2 Summary of contents
Page 1
GS1503B HD Embedded Audio CODEC Data Sheet Features • complies with SMPTE 292M and SMPTE 299M • single chip HD embedded audio solution • operates as an embedded audio multiplexer or demultiplexer • full support for 48kHz synchronous 24-bit audio ...
Page 2
DSCBYPASS De-scrambler & 20 VIN[19:0] Word Alignment 4 VM[3:0] 9 CPUADR[8:0] Host 8 CPUDAT[7:0] Interface 3 CPUCS, CPUWE, CPURE 8 PKT[7:0] PKTEN AIN1/2 AIN3/4 4 AIN5/6 Audio AIN7/8 Input Interface 2 WCINA/B 2 AM[1:0] MUTE Multiplex Mode Block Diagram DSCBYPASS ...
Page 3
Electrical Characteristics ......................................................................................................................... 10 2.1 Absolute Maximum Ratings ....................................................................................................... 10 2.2 DC Electrical Characteristics ..................................................................................................... 10 2.3 AC Electrical Characteristics ..................................................................................................... 11 2.4 Solder Reflow Profiles .................................................................................................................. 13 3. Host Interface .............................................................................................................................................. 14 4. Detailed Description.................................................................................................................................. 17 4.1 Multiplex ...
Page 4
Arbitrary Data Multiplexing in Host Interface Mode ......................................... 43 5. Demultiplex Mode ..................................................................................................................................... 52 5.1 Functional Overview .................................................................................................................... 52 5.2 Video Standard ............................................................................................................................... 53 5.3 Video Input Format ....................................................................................................................... 54 5.3.1 20-bit Scrambled Input .................................................................................................... 54 5.3.2 10-bit Y ...
Page 5
Pin Connections VDD 109 VIN19 110 VIN18 111 VIN17 112 GND 113 VIN16 114 VIN15 115 VIN14 116 VDD 117 VIN13 118 VIN12 119 VIN11 120 GND 121 VIN10 122 VIN9 123 VIN8 124 VDD 125 VIN7 126 VIN6 ...
Page 6
Pin Descriptions Table 1-1: Pin Descriptions Number Symbol Type 1, 14, 27, VDD – 31, 37, 52, 60, 68, 73, 84, 97, 104, 109, 117, 125, 133 2 AIN7 AIN5 AIN3 AIN1/2 I ...
Page 7
Table 1-1: Pin Descriptions (Continued) Number Symbol Type 16, 18, 20, GND – 36, 48, 56, 64, 72, 80, 86, 88, 108, 113, 121, 129, 144 17 ACLKA I 19 ACLKB I 21 ERROR O 22 OPERATE O 23 CRC_ERROR ...
Page 8
Table 1-1: Pin Descriptions (Continued) Number Symbol Type 71, 70, 69, VOUT[19:0] O 67, 66, 65, 63, 62, 61, 59, 58, 57, 55, 54, 53, 51, 50, 49, 47 WCOUTA O 75 WCOUTB O 76 AOUT1 ...
Page 9
Table 1-1: Pin Descriptions (Continued) Number Symbol Type 136 CPU_SEL I 137, 138 AM[1:0] I 139, 140, VM[3:0] I 141, 142 143 RESET I GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 Description Host Interface mode ...
Page 10
Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Supply Voltage Input Voltage (any input) Operating Temperature Storage temperature Lead Temperature (soldering, 10 sec.) 2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics T = 0°C ...
Page 11
AC Electrical Characteristics Table 2-3: AC Electrical Characteristics V = 3.3V ± 5 0°C to 70°C unless otherwise shown Parameter Video Clock Frequency Video Clock Pulse Width Low Video Clock Pulse Width High Video Input ...
Page 12
VCLK Data* * VOUT[19:0], EXTF, EXTH, PKTEN, PKT[7:0] Figure 2-2: Video Data Output Delay & Hold Time t AS ACLKA/B Data* * WCINA, AIN1/2, AIN3/4, WCINB, AIN5/6, AIN7/8 Figure 2-3: Audio Data Input Setup & Hold Time ACLKA/B Data* * ...
Page 13
Solder Reflow Profiles Temperature 230˚C 220˚C 183˚C 150˚C 100˚C 25˚C 120 sec. max 6 min. max Figure 2-6: Maximum Pb-Free Solder Reflow Profile (Preferred) Temperature 260˚C 250˚C 217˚C 200˚C 150˚C 25˚C 60-180 sec. max 8 min. max Figure 2-7: ...
Page 14
Host Interface Table 3-1: Mode A (CPU_SEL set HIGH) Parameter Number Read Cycle Time Read Chip Select Setup Time Read Address Setup Time Read Data Output Delay Time Read Data Hold Time Write Cycle Time Write Chip Select Setup ...
Page 15
Table 3-2: Mode B Read Cycle (CPU_SEL set LOW) Parameter Number Read Address Cycle Time Read Cycle Time Read Enable Setup Time Read Address Setup Time Read Chip Select Setup Time Read Chip Select Hold Time Read Data Output Delay ...
Page 16
CPUADR[1:0] 01 Upper Address CPUDAT[7:0] CPUCS CPUWE Figure 3-3: Host Interface Mode B Write Cycle Timing (CPU_SEL set LOW) Table 3-4: Host Interface Mode B Control Codes CPUADR[1: GS1503B HD ...
Page 17
Detailed Description 4.1 Multiplex Mode 4.1.1 Functional Overview The GS1503B HD Embedded Audio CODEC fully supports the multiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be ...
Page 18
Video Standard The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must ...
Page 19
Video Input Format 4.3.1 10-bit Y and C /C Input Video with TRS and Line Numbers b r GS1503B Y[9:0] VIN[19:10 [9:0] VIN[9:0] +3.3V DSCBYPASS Figure 4-1: Configuration for 10-bit Y and C Numbers ...
Page 20
Y and C /C Input Video With TRS and Line Numbers b r GS1503B Y[9:0] VIN[19:12] VIN[11:10 [9:0] VIN[9:2] VIN[1:0] +3.3V DSCBYPASS Figure 4-3: Configuration for 8-bit Y and C Numbers Y, C ...
Page 21
Y and C The GS1503B will insert TRS and Line Numbers based on EXTF and EXTH inputs. See Figure 4-6 for timing. In progressive format video standards, a high-to-low edge signal must be input at the ...
Page 22
Table 4-5: Register Settings Name Description EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select 8BIT_SEL 0: 10-bit mode select 1: 8-bit mode select DSCBYPASS 0: Descrambling enabled 1: Bypass descrambling 4.3.4 20-bit Scrambled Input GS1503B Y ...
Page 23
Video Output Format 4.4.1 20-bit Scrambled Output GS1503B VOUT[19:0] SCRBYPASS Figure 4-9: Configuration for 20-bit Scrambled Output Table 4-7: Register Settings (Default Mode) Name Description SCRBYPASS 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling 4.4.2 10-bit Y ...
Page 24
Table 4-8: Register Settings Name Description SCRBYPASS 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling 4.5 Video Data Processing 4.5.1 Video Signal Input Detection The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive TRS are ...
Page 25
Video Output CRC Insertion When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS ...
Page 26
Line Number Insertion When LN_INS bit 1 of Host Interface register 008h is set HIGH, the GS1503B will insert line numbers into the video data stream. When set LOW, existing line numbers will remain in the output video stream. ...
Page 27
Audio Data Processing 4.6.1 Digital Audio Input Format The GS1503B will accept two audio input formats, AES/EBU digital audio input and serial input, as listed in Table 4-16. Serial input can be formatted in the following two modes. See ...
Page 28
Digital Audio Input Timing 4.6.2.1 AES/EBU Format Input A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. ACLKA is used to clock the AES/EBU digital audio signal for channels (AIN1/2 and ...
Page 29
Serial Audio Input Modes A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. The GS1503B divides this clock clock the 3.072MHz audio data. An audio word clock at 48kHz (fs) must ...
Page 30
Audio Clock Phase Locked Loop Figure 4-14 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU audio input mode. The GS1503B will internally synchronize the AES/EBU audio input to the corresponding ACLK, using the clock extracted from ...
Page 31
Table 4-18: Register Settings Name Description AUD3/4_DET Ch3/4 Audio input signal detection (1:Detection) AUD1/2_DET Ch1/2 Audio input signal detection (1:Detection) 4.6.5 Audio Channel Status CRC Error Detection In AES/EBU audio mode, the GS1503B will check the Channel Status CRC for ...
Page 32
Audio Channel Status CRC Insert Function When bits 7-4 of Host Interface register 011h are set HIGH, the GS1503B will re-calculate the Channel Status CRC word for the corresponding audio input channel pair. The re-calculated Channel Status CRC word ...
Page 33
Table 4-22: Audio Data Packet Word Descriptions Name No of Words Description ADF 3 Ancillary Data Flag DID 1 Audio Group Data ID DBN 1 Data Block Number DC 1 Data Count CLK 2 Audio Clock Phase Data CH1 4 ...
Page 34
Table 4-24: Register Settings (CASCADE set LOW) Name Description DATAIDA [1-0] Ch1-4 Audio data packet DID setting DATAIDB [1-0] Ch5-8 Audio data packet DID setting When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio ...
Page 35
Video Switching Line Setting The video switching point for field 1 and field 2 can be configured via the GS1503B Host Interface. The SW_LNA[12:0] register is used to configure the video switching line for field 1, and SW_LNB[12:0] to ...
Page 36
Multiplex Cascade Mode Two GS1503B devices can be cascaded in series to allow channels of audio to be multiplexed (only one device requires CASCADE to be set HIGH). the cascade architecture for a 16-channel system. To ...
Page 37
Video Signal before GS1503B (no existing Audio Data Packets) Video Signal before GS1503B (with existing Audio Data Packets) Video Signal after GS1503B Insertion of Audio Groups 1 & 2 (CASCADE = 0) Figure 4-17: Insertion of Audio Groups 1 & ...
Page 38
HANC space or the GS1503B will overwrite existing packets with blanking before multiplexing new packets. See Blank (200 h ) Video Signal before GS1503B (with space between EAV and existing Audio Data Packets) Video ...
Page 39
Table 4-29: Audio Control Packet Word Descriptions Name No of Words ADF 3 DID 1 DBN RATE 1 ACT 1 DEL1-2 3 DEL3-4 3 RSRV 4.10.2 Audio Control Packet DID Setting To ...
Page 40
Table 4-30: Audio Control Packet Group DID Host Interface Settings Audio Group 10-bit Data 1 1E3h 2 2E2h 3 2E1h 4 1E0h Table 4-31: Register Settings Name Description CTRONA Ch1-4 Audio control packet multiplex enable (1: Enabled) CTRIDA[1:0] Ch1-4 Audio ...
Page 41
Table 4-31: Register Settings Name Description DEL1-2B[25:0] Ch5/6 Delay data DEL3-4B[25:0] Ch7/8 Delay data RSRVB[17:0] Ch5-8 Reserved words 4.11 Arbitrary Data Packets The GS1503B can multiplex arbitrary data packets according to SMPTE 291M. Typically, this consists of linear time code ...
Page 42
Arbitrary Data Multiplexing In External Pin Mode This is the default mode for multiplexing arbitrary data packets. The GS1503B will set the PKTENO external pin HIGH when arbitrary data can be input to the device. Two VCLK cycles after ...
Page 43
Arbitrary Data Multiplexing in Host Interface Mode To select this mode, set ARBITMODE bit 0 in Host Interface register 050h HIGH. In this mode, the DID, SDID, DC and User Data Words must be programmed via the corresponding Host ...
Page 44
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item CRC_ERR Video input signal CRC error detection. Set HIGH when a CRC error is detected in the input video signal. This register is refreshed on every video frame. ...
Page 45
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item VBLK_INS Vertical blanking enable. When set HIGH, the output video vertical blanking will be set to 040h for the Luma channel and 200h for the Chroma channel. HBLK_INS ...
Page 46
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item ACRC5/6_INS Ch5/6 audio Channel Status CRC addition. When set HIGH, the Ch5/6 audio input Channel Status CRC is re-calculated before being multiplexed into the Audio Data Packet. Valid ...
Page 47
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item AP1/2_ERR Ch1/2 audio parity error detection. When set HIGH, an audio parity error has been detected in the Ch1/2 audio input. Valid only when AES/EBU audio input format ...
Page 48
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item DATAIDA[1:0] Ch1-4 audio group DID setting. Designates the audio group DID for audio channels See Table or register) is set LOW, the default setting is ...
Page 49
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item RSV Not used. CTRONA Ch1-4 audio control packet multiplex enable. When set HIGH, the audio control packets for audio channels will be multiplexed into the ...
Page 50
Table 4-33: Multiplex Mode Host Interface Registers (Continued) Control Name Description Item ARBITMODE Arbitrary packet mode select. When set HIGH, arbitrary data packets are multiplexed using the Host Interface register settings. When set LOW, arbitrary data packets are multiplexed using ...
Page 51
Table 4-34: Audio Channel Status Default Values Address Value Channel Status 05A 2C Maximum Audio Sample Word Length is 24bits; Encoded Audio Word Length is 24-bit. Others 00 – GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December ...
Page 52
Demultiplex Mode 5.1 Functional Overview The GS1503B HD Embedded Audio CODEC fully supports the demultiplexing of Audio Data Packets, Audio Control Packets and Arbitrary Data Packets as per SMPTE 291M and 299M. The device can be configured to operate ...
Page 53
Video Standard The video standard is selected from the VM[3:0] external pins or VM[3:0] bits 3-0 in Host Interface register 000h. To configure the video standard via the Host Interface, VM_SEL bit 7 in Host Interface register 000h must ...
Page 54
Video Input Format 5.3.1 20-bit Scrambled Input GS1503B Y [19:0] VIN[19:0] DSCBYPASS Figure 5-1: 20-bit Scrambled Input Configuration Table 5-3: Register Settings (Default Mode) Name Description EXT_SEL 0: EXTH/EXTF output select 1: EXTH/EXTF input select ...
Page 55
Y and C /C Input with TRS and Line Numbers b r GS1503B Y[9:0] VIN[19:10 [9:0] VIN[9:0] +3.3V DSCBYPASS Figure 5-2: 10-bit Y and C /C Input with TRS and Line Numbers Configuration ...
Page 56
Video Output Format 5.4.1 10-bit Y and C /C Output b r GS1503B VOUT[19:10] VOUT[9:0] +3.3V SCRBYPASS Figure 5-4: 10-bit Y and C /C Output Configuration b r Table 5-5: Register Settings Name Description SCRBYPASS 0: SMPTE 292M scrambling ...
Page 57
Table 5-6: Register Settings (Default Mode) Name Description SCRBYPASS 0: SMPTE 292M scrambling enabled 1: Bypass SMPTE 292M scrambling 5.5 Video Data Processing 5.5.1 Video Signal Input Detection The GS1503B will set the VIDEO_DET external pin HIGH when three consecutive ...
Page 58
Video Output CRC Insertion When the CRC_INS bit 4 of Host Interface register 000h is set HIGH, the GS1503B will re-calculate the video line CRC words. The re-calculated CRC words are inserted in the video output signal. When CRC_INS ...
Page 59
TRS Word Insertion When TRS_INS bit 0 of Host Interface register 008h is set HIGH, the GS1503B will insert TRS codes into the video data stream. When set LOW, existing TRS codes will remain in the output video stream. ...
Page 60
WCOUTA/WCOUTB MSB 23 MODE0 LSB 0 MODE1 MODE2 Sync 24-bit Audio Sample Word Preamble (AES/EBU) Figure 5-6: Audio Output Formats 5.6.2 Digital Audio Output Timing 5.6.2.1 AES/EBU Format Output A 6.144MHz (128fs) audio clock must be supplied ...
Page 61
Table 5-15: Register Settings Name Description CS_MODE 0: Audio Channel Status replace 1: Audio Channel Status demultiplex CH_SEL[2:0] Audio Channel Status select Y [19:0] 6.144MHz (128 fs) 6.144MHz (128 fs) 6.144MHz ACLKA/B AOUT1/2, AOUT3/4 AOUT5/6, AOUT7/8 ...
Page 62
Serial Audio Output Modes A 6.144MHz (128fs) audio clock must be supplied to the ACLKA and ACLKB inputs. An audio word clock at 48kHz (fs) will be output at the WCOUTA and WCOUTB external pins, as shown in Figure ...
Page 63
Audio Clock Phase Locked Loop Figure 5-9 shows the configuration for deriving the 6.144MHz audio clock in AES/EBU and serial audio output modes. The GS1503B will internally synchronize the audio output to the corresponding ACLK. This configuration is not ...
Page 64
Audio Data Packet Detection The audio data packet detect registers will be set HIGH when a corresponding audio group DID has been detected in the Chroma channel of the input video stream. Host Interface register 013h, bits 7-4, report ...
Page 65
Table 5-17: Register Settings Name Description ECCB_ERR Ch5-8 Audio data packet ECC error detection (1: Detection) ECCA_ERR Ch1-4 Audio data packet ECC error detection (1: Detection) CORRECTB[11:0] Ch5-8 correctable packets in one video frame NO_CORRECTB[11:0] Ch5-8 un-correctable packets in one ...
Page 66
Table 5-18: Register Settings Name Description DBNB_ERR Ch5-8 Audio data packet DBN error detection (1:Detection) ADPB8B_ERR Ch5-8 Audio data packet bit8 error detection (1:Detection) ADPCSB_ERR Ch5-8 Audio data packet CS error detection (1:Detection) DBNA_ERR Ch1-4 Audio data packet DBN error ...
Page 67
When CASCADE is set HIGH (external pin or register), the GS1503B will default to audio groups 3 and 4, where AOUT1/2 and AOUT3/4 will be demultiplexed from audio data packets with group 3 DID, and AOUT5/6 and AOUT7/8 will be ...
Page 68
Table 5-22: Register Settings Name Description CASCADE Cascade enable (1: Enabled) 5.8 Audio Control Packets 5.8.1 Audio Control Packet Detection The audio control packet detect registers will be set HIGH when a corresponding audio group DID has been detected in ...
Page 69
Table 5-24: Audio Control Packet Group DID Host Interface Settings Audio Group 10-bit Data 1 1E3h 2 2E2h 3 2E1h 4 1E0h Table 5-25: Register Settings Name Description CTRONA Ch1-4 Audio control packet demultiplex enable (1: Enabled) CTRIDA[1:0] Ch1-4 Audio ...
Page 70
Table 5-25: Register Settings Name Description ASXB Ch5-8 Synchronization (0: Synchronous; 1: Non-synchronous) DEL1-2B[25:0] Ch5/6 Delay data DEL3-4B[25:0] Ch7/8 Delay data RSRVB[17:0] Ch5-8 Reserved words 5.9 Arbitrary Data Packets The GS1503B can demultiplex arbitrary data packets according to SMPTE 291M. ...
Page 71
Arbitrary Data Demultiplexing in External Pin Mode This is the default mode for demultiplexing arbitrary data packets. The GS1503B will set the PKTEN external pin HIGH before arbitrary data will be output. Two VCLK cycles after PKTEN goes HIGH, ...
Page 72
Table 5-26: Register Settings Name Description ARBITON Arbitrary packet demultiplex enable (1: Enabled) Valid only when ARBITMODE is HIGH ARBITMODE Arbitrary packet mode selection (0: External pin mode; 1: Host mode) ARBITDID[7-0] Arbitrary packet DID setting ARBITSDID[7-0] Arbitrary packet SDID ...
Page 73
Table 5-27: Register Settings Name Description ANCI Ancillary data packet delete (1: Deletion enabled) DEL_SEL Ancillary data packet delete mode select (0: Entire data delete; 1: Group designated data delete) ADPG4_DEL Audio group 4 data packet delete (1: Delete) ADPG3_DEL ...
Page 74
Table 5-28: Register Settings Name Description MUXERRB Ch5-8 embedded clock phase information error detect (1: Detected) MUXERRA Ch1-4 embedded clock phase information error detect (1: Detected) HD Audio Embedding Module Y [19:0] VIN[19:0] Audio Channels 1 ...
Page 75
Table 5-29: Demultiplex Mode Host Interface Registers Control Name Description Item Video VM_SEL Video input format (external pin/internal register) configuration select. When set LOW, the video input format is configured via the VM[3:0] pins. format is configured via the "VM[3:0]" ...
Page 76
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item HBLK_INS Horizontal blanking enable. When set HIGH, the output video horizontal blanking, including TRS, line numbers and line CRC words, will be set to 040h for the Luma ...
Page 77
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item Audio AUDIO_CS[7:0] Audio Channel Status. When "CS_MODE" is set Channel HIGH, the 23 8-bit bytes of the Audio Channel : Status Status Block, as defined in AES3-1992, are ...
Page 78
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item ADPG2_DET Audio group 2 data packet detect. When set HIGH, audio data packets with group 2 DID have been detected in the incoming Chroma video data stream. NOTE: ...
Page 79
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item DATAIDB[1:0] Ch5-8 audio group DID setting. Designates the audio group DID for audio channels See Table register) is set LOW, the default setting is audio ...
Page 80
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item NO_CORRECTB Ch5-8 ECC un-correctable packets. Designates the number of audio data packets for channels [11:0] that could not be corrected in one video frame using ...
Page 81
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item ASXB Ch5-8 synchronization. When set HIGH, the "asx" bit of the audio control packet RATE word designates audio channels asynchronous, as per SMPTE 299M. ...
Page 82
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item DEL3-4A[25:0] Ch3/4 delay data. Designates the accumulated audio processing delay relative to video for audio channels 3 and 4. RSRVA[17:0] Ch1-4 reserve words. Designates the value set in ...
Page 83
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item Packet RSV Not used. Delete ANCI Ancillary data delete. When set HIGH, all ancillary data packets ("DEL_SEL" is LOW) or ancillary data packets with DIDs designated in Host ...
Page 84
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item ACPG2_DEL Audio group 2 control packet delete. When set HIGH, all audio control packets with group 2 DID will be deleted from the Luma video data stream. Valid ...
Page 85
Table 5-29: Demultiplex Mode Host Interface Registers (Continued) Control Name Description Item ARBITLINEA Field 1 arbitrary packet demultiplex line number setting. Designates the field 1 video line from [11:0] which the arbitrary data packets will be demultiplexed. Valid only when ...
Page 86
Using the GS1503B with the GS4911B or GS4910B In Serial Audio multiplex mode, the GS4911B or GS4901B can be used to provide clocks for the input audio. Figure 6-1 shows this arrangement. Video Chain GS49X1B MCLK ...
Page 87
References & Bibliography SMPTE 260M 1999 1125/60 High-Definition Production System - Digital Representation and Bit-Parallel Interface SMPTE 274M 1998 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates SMPTE 291M 1998 Ancillary Data Packet ...
Page 88
Packaging & Ordering Information 8.1 Package Dimensons 18.0 ± 0.4 16.0 ± 0.1 108 109 INDEX 144 1 0.13-0.23 0.4 8.2 Packaging Data Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, θ j-c Junction to Air ...
Page 89
... Ordering Information Part Number Package GS1503BCVE2 144 pin TQFP GS1503B HD Embedded Audio CODEC Data Sheet 37953 - 1 December 2009 Temperature Pb-Free RoHS-Compliant 0°C to 70°C Yes Yes ...
Page 90
Revision History Version ECR Date 1 153293 December 2009 0 139048 August 2006 DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve ...