GAL16LV8C-10LJN LATTICE [Lattice Semiconductor], GAL16LV8C-10LJN Datasheet

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GAL16LV8C-10LJN

Manufacturer Part Number
GAL16LV8C-10LJN
Description
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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• HIGH PERFORMANCE E
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E
• EIGHT OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
The GAL16LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E
bines CMOS with Electrically Erasable (E
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-
tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16lv8_05
Features
Description
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— 100% Functional Testability
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
(GAL16LV8C)
®
Advanced CMOS Technology
2
CMOS
2
®
CMOS process, which com-
TECHNOLOGY
2
) floating gate technology.
1
Functional Block Diagram
Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
I
I
I
4
6
8
I
9
I
GND
GAL16LV8
2
I
Low Voltage E
Top View
I/CLK
PLCC
I/OE
11
Generic Array Logic™
GAL16LV8
I/O/Q
Vcc
20
8
8
8
8
8
8
8
8
CLK
I/O/Q
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
I/O/Q
13
18
14
16
2
CMOS PLD
OE
August 2004
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE

Related parts for GAL16LV8C-10LJN

GAL16LV8C-10LJN Summary of contents

Page 1

... LEAD-FREE PACKAGE OPTIONS Description The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3. CMOS process, which com- bines CMOS with Electrically Erasable (E High speed erase times (< ...

Page 2

... Part Number Description GAL16LV8D Device Name GAL16LV8C Speed (ns Low Power Power ...

Page 3

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC ...

Page 4

Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture configurations available in this mode are similar to the common 16R8 and 16RP4 devices with various permutations of polarity, I/O and register ...

Page 5

Registered Mode Logic Diagram 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 PLCC Package Pinout 2128 ...

Page 6

Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions. Architecture configurations available in this mode are similar to the common 16L8 and 16P8 devices with programmable polarity in each macrocell six I/Os ...

Page 7

Complex Mode Logic Diagram 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 PLCC Package Pinout 2128 ...

Page 8

Simple Mode In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. Architecture configurations available in this mode are similar to the common 10L8 and 12P6 devices with many permutations of ge- neric ...

Page 9

Simple Mode Logic Diagram 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 Specifications GAL16LV8 PLCC Package Pinout 2128 ...

Page 10

Absolute Maximum Ratings Supply voltage V ................................... –0.5 to +4.6V CC Input voltage applied ................................ –0.5 to +5.6V I/O voltage applied ................................... –0.5 to +4.6V Off-state output voltage applied ............... –0.5 to +4.6V Storage Temperature ................................ –65 to 150°C Ambient ...

Page 11

AC Switching Characteristics TEST DESCRIPTION PARAMETER COND Input or I/O to Combinational Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, ...

Page 12

... Supply Current f toggle 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and T Specifications GAL16LV8C Recommended Operating Conditions (1) Commercial Devices: Ambient Temperature (T Supply voltage (V with Respect to Ground ...

Page 13

... Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (T = 25° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL16LV8C COM -7 MIN. MAX — — 0 — ...

Page 14

Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL16LV8 INPUT or I/O FEEDBACK ...

Page 15

Descriptions max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and ...

Page 16

... GAL16LV8C: Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL16LV8C Output Load Conditions (see figure) Test Condition 316Ω B Active High 316Ω ...

Page 17

Electronic Signature An electronic signature is provided in every GAL16LV8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always ...

Page 18

Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL16LV8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q t outputs set low after a specified time ( ...

Page 19

GAL16LV8D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 PT H->L 1.05 PT L->H 1 0.95 0.9 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 ...

Page 20

GAL16LV8D: Typical AC and DC Characteristic Diagrams Vol vs Iol 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 0.00 10.00 20.00 30.00 40.00 Iol (mA) Normalized Icc vs Vcc 1.10 1.05 1.00 0.95 0.90 0.85 3.00 3.15 3.30 ...

Page 21

... GAL16LV8C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0 Number of Outputs Switching Delta Tpd vs Output Loading 34 30 RISE 26 22 FALL ...

Page 22

... GAL16LV8C: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.8 0.6 0.4 0.2 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vin (V) Specifications GAL16LV8 Voh vs Ioh 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 Ioh (mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Input Clamp (Vik) ...

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