GAL20VP8B-15LP LATTICE [Lattice Semiconductor], GAL20VP8B-15LP Datasheet

GAL20VP8B-15LP

Manufacturer Part Number

GAL20VP8B-15LP

Description

High-Speed E2CMOS PLD Generic Array Logic

Manufacturer

LATTICE [Lattice Semiconductor]

Datasheet

1.GAL20VP8B-15LP.pdf (17 pages)

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• HIGH DRIVE E

• ENHANCED INPUT AND OUTPUT FEATURES

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL20VP8, with 64 mA drive capability and 15 ns maximum

propagation delay time is ideal for Bus and Memory control appli-

cations.

Semiconductor's advanced E

CMOS with Electrically Erasable (E

speed erase times (<100ms) allow the devices to be reprogrammed

quickly and efficiently.

System bus and memory interfaces require control logic before

driving the bus or memory interface signals. The GAL20VP8

combines the familiar GAL20V8 architecture with bus drivers as

its outputs. The generic architecture provides maximum design flex-

ibility by allowing the Output Logic Macrocell (OLMC) to be con-

figured by the user. The 64mA output drive eliminates the need for

additional devices to provide bus-driving capability.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20vp8_03

Features

Description

— TTL Compatible 64 mA Output Drive

— 15 ns Maximum Propagation Delay

— Fmax = 80 MHz

— 10 ns Maximum from Clock Input to Data Output

— UltraMOS

— Schmitt Trigger Inputs

— Programmable Open-Drain or Totem-Pole Outputs

— Active Pull-Ups on All Inputs and I/O pins

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Compatible with Standard GAL20V8

— 100% Functional Testability

— Ideal for Bus Control & Bus Arbitration Logic

— Bus Address Decode Logic

— Memory Address, Data and Control Circuits

— DMA Control

CELL TECHNOLOGY

The GAL20VP8 is manufactured using Lattice

Advanced CMOS Technology

CMOS

GAL

CMOS process which combines

DEVICE

) floating gate technology. High

Functional Block Diagram

Pin Configuration

Vcc

I/CLK

GAL20VP8

Top View

PLCC

High-Speed E

I/O/Q

GND

I/O/Q

GAL20VP8

Generic Array Logic™

I/CLK

I/OE

Vcc

OLMC

IMUX

20VP8

December 1997

DIP

GAL

CLK

CMOS PLD

I/O/Q

I/OE

I/O/Q

GND

I/O/Q

Related parts for GAL20VP8B-15LP

GAL20VP8B-15LP Summary of contents

Page 1

Features • HIGH DRIVE E 2 CMOS ® GAL ® DEVICE — TTL Compatible 64 mA Output Drive — Maximum Propagation Delay — Fmax = 80 MHz — Maximum from Clock Input to Data Output — ...

... Tsu (ns) Tco (ns) Icc (mA Part Number Description GAL20VP8B Device Name Speed (ns Low Power Power Ordering # 115 GAL20VP8B-15LP 115 GAL20VP8B-15LJ 115 GAL20VP8B-25LP 115 GAL20VP8B-25LJ _ XXXXXXXX Specifications GAL20VP8 Package 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC ...

Page 3

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC ...

Page 4

Registered Mode In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. All registered macrocells share common clock and output enable control pins. Any macrocell can be configured as registered ...

Page 5

Registered Mode Logic Diagram 1(2) 0 0000 0280 2(3) 0320 0600 3(4) 0640 0920 4(5) 0960 1240 5(6) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) 64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 Byte6 ...

Page 6

Complex Mode In the Complex mode, macrocells are configured as output only or I/O functions six I/Os are possible in this mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The two outer ...

Page 7

Complex Mode Logic Diagram 1( 0000 0280 2(3) 0320 0600 3(4) 0640 0920 4(5) 0960 1240 5(6) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) 64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 ...

Page 8

Simple Mode In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each ...

Page 9

Simple Mode Logic Diagram 1( 0000 0280 2(3) 0320 0600 3(4) 0640 0920 4(5) 0960 1240 5(6) 1280 1560 7(9) 1600 1880 8(10) 1920 2200 9(11) 2240 2520 10(12) 11(13) 64-USER ELECTRONIC SIGNATURE FUSES 2568, 2569, .... Byte7 ...

Page 10

Absolute Maximum Ratings Supply voltage V ........................................ –.5 to +7V CC Input voltage applied .......................... –2 Off-state output voltage applied ......... –2 Storage Temperature ................................ –65 to 150 C Ambient Temperature with Power Applied ........................................... –55 ...

Page 11

AC Switching Characteristics TEST DESCRIPTION PARAMETER 1 COND . Input or I/O to Combinational Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, Input or ...

Page 12

Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL20VP8 INPUT or I/O FEEDBACK ...

Page 13

Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY max with No ...

Page 14

Electronic Signature An electronic signature word is provided in every GAL20VP8 de- vice. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision num- bers, or inventory control. The signature ...

Page 15

Power-Up Reset INTERNAL REGISTER FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL20VP8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- t puts set low after a specified time ( pr, 1 ...

Page 16

Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 ...

Page 17

Typical AC and DC Characteristic Diagrams Vol vs Iol 0.5 0.4 0.3 0.2 0.1 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta ...

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