GAL22LV10C-10LJ LATTICE [Lattice Semiconductor], GAL22LV10C-10LJ Datasheet

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GAL22LV10C-10LJ

Manufacturer Part Number
GAL22LV10C-10LJ
Description
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet

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• HIGH PERFORMANCE E
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL22LV10D, at 4 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL22LV10C can interface with both 3.3V and 5V
signal levels. The GAL22LV10 is manufactured using Lattice
Semiconductor's advanced 3.3V E
bines CMOS with Electrically Erasable (E
ogy. High speed erase times (<100ms) allow the devices to be
reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write
cycles and data retention in excess of 20 years are specified.
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
22lv10_03
DESCRIPTION
FEATURES
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— 100% Functional Testability
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
(GAL22LV10C)
®
Advanced CMOS Technology
2
CMOS
2
CMOS process, which com-
®
TECHNOLOGY
2
) floating gate technol-
1
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
I/CLK
I
I
I
I
I
I
I
I
I
I
I
NC
I
I
I
I
I
I
11
5
7
9
12
4
GAL22LV10
Low Voltage E
14
2
Top View
GAL22LV10
PLCC
Generic Array Logic™
28
16
PRESET
RESET
10
12
14
16
16
12
10
14
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
26
18
25
23
21
19
2
CMOS PLD
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
July 1997
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

Related parts for GAL22LV10C-10LJ

GAL22LV10C-10LJ Summary of contents

Page 1

... ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The GAL22LV10D maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice 2 Semiconductor's advanced 3.3V E CMOS process, which com- bines CMOS with Electrically Erasable (E ogy. High speed erase times (< ...

Page 2

... PART NUMBER DESCRIPTION GAL22LV10D Device Name GAL22LV10C Speed (ns Low Power Power Specifications GAL22LV10 ...

Page 3

OUTPUT LOGIC MACROCELL (OLMC) The GAL22LV10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and ...

Page 4

REGISTERED MODE ACTIVE LOW COMBINATORIAL MODE ACTIVE LOW Specifications GAL22LV10 ...

Page 5

GAL22LV10 LOGIC DIAGRAM / JEDEC FUSE MAP 0000 0044 . . . 0396 0440 . . . . 0880 3 0924 . . . . . 1452 4 1496 . . . . . . 2112 ...

Page 6

ABSOLUTE MAXIMUM RATINGS Supply voltage V .................................... -0.5 to +4.6V CC Input voltage applied ................................. -0.5 to +5.6V I/O voltage applied .................................... -0.5 to +4.6V Off-state output voltage applied................. -0.5 to +4.6V Storage Temperature .................................. -65 to 150 C Ambient ...

Page 7

AC SWITCHING CHARACTERISTICS TEST DESCRIPTION PARAMETER COND Input or I/O to Combinational Output Clock to Output Delay — Clock to Feedback Delay t su — Setup Time, ...

Page 8

... Supply Current f toggle 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and T Specifications GAL22LV10C Specifications GAL22LV10 (1) RECOMMENDED OPERATING COND. Commercial Devices: 0.5 to +5.6V - ...

Page 9

... Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Description section. 4) Refer to fmax Description section. CAPACITANCE ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL22LV10C Specifications GAL22LV10 Over Recommended Operating Conditions TYPICAL UNITS COM COM COM -7 -10 -15 MIN ...

Page 10

SWITCHING WAVEFORMS INPUT or I/O FEEDBACK COMBINATORIAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O ...

Page 11

DESCRIPTIONS CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY max with No Feedback ...

Page 12

... B High Z to Active High at 1.9V High Z to Active Low at 1.0V C Active High to High Z at 1.9V Active Low to High Z at 1.0V GAL22LV10C: SWITCHING TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level ...

Page 13

ELECTRONIC SIGNATURE An electronic signature (ES) is provided in every GAL22LV10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always ...

Page 14

POWER-UP RESET INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Circuitry within the GAL22V10 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low ...

Page 15

GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 ...

Page 16

GAL22LV10D: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 1 0.8 0.6 0.4 0.2 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00 Iol (mA) Normalized Icc vs Vcc 1.40 1.20 1.00 0.80 0.60 3.00 3.15 3.30 3.45 Supply Voltage ...

Page 17

... GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.1 -0.2 -0.3 -0.4 -0 Number of Outputs Switching Delta Tpd vs Output Loading 28 24 RISE 20 FALL ...

Page 18

... GAL22LV10C: TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 1 0.8 0.6 0.4 0.2 0 0.00 10.00 20.00 30.00 40.00 Iol (mA) Normalized Icc vs Vcc 1.40 1.20 1.00 0.80 0.60 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vin (V) Specifications GAL22LV10 Voh vs Ioh 0.00 5.00 10.00 15.00 20.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Input Clamp (Vik) ...

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