FDC37B78X SMSC Corporation, FDC37B78X Datasheet
FDC37B78X
Related parts for FDC37B78X
FDC37B78X Summary of contents
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... Asynchronous Access to Two Data - Registers and One Status Register - Supports Interrupt and Polling Access 8 Bit Timer/Counter - - Port 92 Support FDC37B78x ADVANCE INFORMATON FEATURES - Fast Gate A20 and Hardware Keyboard Reset Real Time Clock - Day of Month Alarm, Century Byte MC146818 and DS1287 Compatible ...
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Drivers and Schmitt Trigger Inputs Enhanced FDC Digital Data Separator Low Cost Implementation - No Filter Components Required - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, - 250 Kbps Data Rates Programmable Precompensation - Modes Serial Ports ...
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FEATURES.......................................................................................................................... 1 GENERAL DESCRIPTION................................................................................................... 5 DESCRIPTION OF PIN FUNCTIONS .................................................................................. 7 BUFFER TYPE DESCRIPTIONS........................................................................................12 REFERENCE DOCUMENTS ..............................................................................................14 FUNCTIONAL DESCRIPTION ............................................................................................15 SUPER I/O REGISTERS.................................................................................................15 HOST PROCESSOR INTERFACE..................................................................................15 FLOPPY DISK CONTROLLER ...........................................................................................16 FDC INTERNAL REGISTERS......................................................................................16 COMMAND SET/DESCRIPTIONS...............................................................................41 Force Write Protect ......................................................................................................70 SERIAL ...
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ACPI REGISTERS .....................................................................................................157 CONFIGURATION............................................................................................................169 SYSTEM ELEMENTS....................................................................................................169 Entering the Configuration State.................................................................................170 Exiting the Configuration State...................................................................................170 CONFIGURATION SEQUENCE ................................................................................170 CONFIGURATION REGISTERS.......................................................................................172 Chip Level (Global) Control/Configuration Registers [0x00-0x2F] ...............................176 Logical Device Configuration/Control Registers [0x30-0xFF] ......................................180 Logical Device Registers............................................................................................180 I/O Base Address Configuration Register ...
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... Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows underflow Through internal configuration registers, each of the FDC37B78x 's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 12 IRQ options or Serial IRQ The parallel option, and four DMA channel options for each logical device ...
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... Pin QFP nDTR1 117 nRI1 118 nDCD1 119 nRI2 120 VCC 121 nDCD2 122 RXD2/IRRX 123 TXD2/IRTX 124 nDSR2 125 nRTS2 126 nCTS2 127 nDTR2 128 FIGURE 1 - FDC37B78x PIN CONFIGURATION FDC37B78x 6 IOCHRDY VCC 62 DRQ3 61 nDACK3 60 DRQ2 59 nDACK2 58 DRQ1 57 nDACK1 56 DRQ0 55 nDACK0 54 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (40) 44-47, System Data Bus 49-52 23-38 16-bit System Address Bus 43 Address Enable 64 I/O Channel Ready 53 ISA Reset Drive 40 Serial IRQ/IRQ15 39 PCI Clock/IRQ14/GP50 55 DMA Request ...
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PIN No./QFP NAME 62, 93, +5V Supply Voltage 121 7, 48, Digital Ground 74, 104 67 Analog Ground 69 Trickle Supply Voltage 65 Battery Voltage 19 Power On 20 Button In 21 Power Management Event/SCI/IRQ9 16 Read Disk Data 11 ...
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PIN No./QFP NAME 2 Drive Density Select 1/GP52/IRQ8/nSMI GENERAL PURPOSE I/O (6) 77 General Purpose 10/nSMI 78 General Purpose 11/nRING/EETI 79 General Purpose 12/WDT/P17/EETI 80 General Purpose 13/LED Driver 81 General Purpose 14/Infrared Rx 82 General Purpose 15/Infrared Tx (Note ...
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PIN No./QFP NAME 119 Data Carrier Detect 1 118 Ring Indicator 1 SERIAL PORT 2 INTERFACE (8) 123 Receive Serial Data 2/Infrared Rx 124 Transmit Serial Data 2/Infrared Tx (Note 3) 126 Request to Send 2 127 Clear to Send ...
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PIN No./QFP NAME 75 Keyboard Reset 76 Gate A20 Note 1 The “n” as the first letter of a signal name indicates an “Active Low” signal. Note 2 KBDRST is active low. Note 3 This pin defaults to an output ...
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BUFFER TYPE DESCRIPTIONS SYMBOL I Input, TTL compatible. IS Input with Schmitt trigger. ICLK RTC 32.768 kHz crystal input. OCLK RTC 32.768 kHz crystal output. IO4 Input/Output, 4mA sink, 2mA source. O4 Output, 4mA sink, 2mA source. O8 Output, 8mA ...
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... SA[0:15] SD[O:7] HOST DRQ[0:3] CPU INTERFACE nDACK[0:3] TC IRQ[1,3-12,14] RESET_DRV IOCHRDY nINDEX nTRK0 nDSKCHG nWRPRT nWGATE Vtr Vss Vcc FIGURE 2 - FDC37B78x BLOCK DIAGRAM nSMI* nROMOE* BIOS nROMCS* nSMI BUFFER RD[0:7]* DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL BUS WDATA WCLOCK SMSC PROPRIETARY DIGITAL DATA 82077 ...
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GENERAL PURPOSE I/O PINS TABLE 2 - GENERAL PURPOSE I/O PIN FUNCTIONS PIN NO. DEFAULT ALT QFP FUNCT FUNCT 1 77 GPIO nSMI 78 GPIO nRING 79 GPIO WDT 80 GPIO LED 81 GPIO IRRX2 82 GPIO IRTX2 4 nMTR1 ...
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... Base + (0-1) Note 1: Refer to the configuration register descriptions for setting the base address HOST PROCESSOR INTERFACE The host processor communicates with the FDC37B78x through a series of read/write registers. The port addresses for these registers are shown in Table 4. accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. (Always 1) BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. (Always 1) ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE TAPE SEL1 (TDR. The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any ...
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TABLE 8 - INTERNAL 2 DRIVE DECODE - NORMAL DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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TABLE 11 - PRECOMPENSATION DELAYS PRECOMP DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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TABLE 13 - DRVDEN MAPPING DT1 DT0 DRVDEN1 ( DRATE0 1 0 DRATE0 0 1 DRATE0 1 1 DRATE1 TABLE 14 - DEFAULT PRECOMPENSATION DELAYS DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps DRVDEN0 ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any 7 6 NON DMA RQM DIO BIT 0 ...
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An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by TABLE 15 - FIFO SERVICE DELAY FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes FIFO ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a ...
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PS/2 Mode 7 DSK CHG RESET N/A N/A COND. BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. BITS 1 ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 14 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 14 ...
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TABLE 16 - STATUS REGISTER 0 BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check Head Address 1,0 DS1,0 Drive Select DESCRIPTION 00 - Normal termination of command. The specified ...
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TABLE 17 - STATUS REGISTER 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable WP pin became a "1" while the ...
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TABLE 18 - STATUS REGISTER 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a ...
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Model 30 mode - (IDENT low, MFM low) This mode supports PS/2 configuration and register set. The DMA enable bit of the DOR becomes valid (FINTR and DRQ can active high and DENSEL is active ...
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FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read ...
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FDC will continue to complete the sector hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal termination" result status. status indications can be ignored if ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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SYMBOL NAME H/HDS Head Address Selected head (disk side encoded in the sector ID field. HLT Head Load Time The time interval that FDC waits after loading the head and before initializing a ...
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TABLE 21 - DESCRIPTION OF COMMAND SYMBOLS OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative Cylinder Number SC Number of Sectors Per Track SK Skip Flag SRT Step Rate ...
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INSTRUCTION SET PHASE R Command W MT MFM Execution Result TABLE 22 - INSTRUCTION SET READ DATA DATA BUS D5 D4 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W RECALIBRATE DATA BUS D5 ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result LOCK RELATIVE SEEK DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. ...
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TABLE 25 - SKIP BIT VS READ DATA COMMAND DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED SECTOR READ? 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data RESULTS CM BIT OF DESCRIPTION ST2 SET? OF RESULTS ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. TABLE 26 - SKIP BIT VS. READ DELETED ...
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TABLE 27 - RESULT PHASE TABLE FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT ...
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Because data is not transferred to the host, TC (pin 89) cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when ...
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This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the IDX pin again and it terminates the command. SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 80x ...
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TABLE 29 - TYPICAL VALUES FOR FORMATTING FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status Terminate the Seek command 3) Read ID - Verify head ...
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TABLE 31 - DRIVE CONTROL DELAYS (MS 500K 0 64 128 256 112 224 F 60 120 240 0 ...
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Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value returned as the result byte. Relative Seek The command is coded the same as for ...
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Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the ...
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The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. 2. The write pre-compensation given to a perpendicular mode drive will be 0ns. 3. For D0-D3 programmed conventional mode drives any ...
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LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain ...
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The chip incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. rates are independently programmable from 460.8K ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 2 Setting this bit to ...
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TABLE 34 - INTERRUPT CONTROL FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORIT BIT 3 BIT 2 BIT 1 BIT 0 Y LEVEL Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When ...
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FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 ...
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Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input ...
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Table 35 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k ; Using 3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 50 2304 ...
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Effect Of The Reset on Register File The Reset Function Table (TABLE 36) details the effect of the Reset input on each of the registers of the Serial Port. FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts ...
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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, ...
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TABLE 36 - RESET FUNCTION REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read ...
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TABLE 37 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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TABLE 38 - REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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GP11 and GP62. This feature is enabled onto the nRING pin or one of the ring indicator pins (nRI1, nRI2) via the Ring Filter Select Register defined below. If enabled, a frequency ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. The IR ...
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This chip incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration information on disabling, ...
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TABLE 39 - PARALLEL PORT CONNECTOR HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects ...
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EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bi- directional modes are also available EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the ...
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EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that ...
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Write Sequence of Operation 1. The host sets PDIR bit in the control register to a logic "0". nWRITE. 2. The host selects an EPP register, places data on the SData bus and drives nIOW active. 3. The chip places ...
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TABLE 40 - EPP PIN DESCRIPTIONS EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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The bit map of the Extended Parallel Port registers is data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 0 0 cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB compress intrValue ecr MODE Note 1: These registers are available ...
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TABLE 41 - ECP PIN DESCRIPTIONS NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition to TABLE 42 - ECP REGISTER DEFINITIONS ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...
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BIT 7 compress This bit is read only. During a read low level. This means that this chip does not support hardware RLE compression. support hardware de-compression! BIT 6 intrValue Returns the value on the ISA IRq ...
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TABLE 44 - EXTENDED CONTROL REGISTER R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data ...
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FIFO does not cross the threshold. The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the ...
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The only way to properly terminate DMA transfers is with a TC.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed ...
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Otherwise it may be writeIntrThreshold bytes. writeIntrThreshold = (16-<threshold>) free bytes in FIFO An interrupt is generated when serviceIntr is 0 filled with and the number of bytes in the FIFO ...
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PARALLEL PORT FLOPPY DISK CONTROLLER The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes ...
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TABLE 47 - FDC PARALLEL PORT PINS SPP MODE PIN DIRECTION nSTROBE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 nACK BUSY PE SLCT nALF nERROR nINIT nSLCTIN Note 1: These pins are outputs in mode PPFD2, inputs in mode ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management Direct power management ...
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Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert ...
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TABLE 48 - PC/AT AND PS/2 AVAILABLE REGISTERS AVAILABLE REGISTERS BASE + PC-AT ADDRESS Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. TABLE 50 - STATE OF FLOPPY DISK DRIVE INTERFACE PINS IN POWERDOWN FDD PINS nRDATA ...
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... The RTC and CMOS registers are also battery backed up. configuration of the Consumer IR wake-up functionality is not battery backed-up. V Support TR The FDC37B78x requires trickle supply ( provide sleep TR programmable wake-up events in the Soft Power Management logic, SCI, PME and SMI interfaces when V is removed ...
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... Standby Clock Output The FDC37B78x provides a 32.768 kHz trickle clock output pin. This output is active as long as V present. Note wake-up events when its full minimum potential at least 10 s cycles on before V begins a power-on cycle. When V ...
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... SERIAL INTERRUPTS The FDC37B78x will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. Timing Diagrams For IRQSER Cycle PCICLK = 33Mhz_IN pin IRQSER = SIRQ pin A) Start Frame timing with source sampled a low pulse on IRQ1 ...
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... S=Sample I= Idle. Controller will drive the IRQSER back high for one clock, then tri-state. Any IRQSER Device (i.e., The FDC37B78x) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the IRQSER is already in an IRQSER ...
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... IRQSER Cycle’s mode. IRQSER Data Frame Once a Start Frame has been initiated, the FDC37B78x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase ...
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IRQSER PERIOD Note the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. The ...
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Stop Cycle Control Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low ...
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The chip contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS must be tied high or pulled up to Vcc with a resistor so as not to ...
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... GENERAL PURPOSE I/O The FDC37B78x provides a set of flexible Input/Output control functions to the system designer through the 21 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform simple I/O or can be individually configured to provide predefined alternate functions. Power-On-Reset configures all GPIO pins as non-inverting inputs. ...
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... Note 1: These registers can also be accessed through the configuration registers L8 - CRxx, as shown, when the FDC37B78x is in the configuration state. and Data port addresses are used to access the GPIO data, Soft Power Status and Enable, and the Watchdog Timer Control registers. ...
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... Each GPIO port has an 8-bit configuration register that controls the behavior of the pin. The GPIO configuration registers are only accessible when the FDC37B78x is in the Configuration state; more information can be found in the Configuration section of this specification. Each GPIO port may be configured as either an input or an output ...
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TABLE 55 - GPIO CONFIGURATION SUMMARY SELECTED DIRECTION FUNCTION BIT B0 GPIO ALT. X Note 1. For alternate function selects, the pin direction is set and controlled internally; i.e., regardless of ...
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GPIO OPERATION The operation of the GPIO ports is illustrated in FIGURE 3. purposes only and is not intended to suggest specific implementation details. FIGURE 3 - GPIO FUNCTION ILLUSTRATION D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO ...
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When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or non-inverted logic value present at the GPIO pin. GPIO port that is programmed as an input has no effect. ...
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... P11 Keyboard and Mouse Interface KIRQ is the Keyboard IRQ MIRQ is the Mouse IRQ Port 21 is used to create a GATEA20 signal from the FDC37B78x. concentrates on the enhancements to the 8042. For general information about the 8042, refer to The the "Hardware Description of the 8042" in the 8- Bit Embedded Controller Handbook ...
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... This bit read only register. Refer to the description of the Status Register for more information. CPU-to-Host Communication The FDC37B78x CPU can write to the Output Data register this register automatically sets Bit 0 (OBF) in the Status register. See Table 58. Table 58 - Host Interface Flags ...
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... If "EN FLAGS" has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be connected to system interrupt to signify that the FDC37B78x CPU has written to the output data register via "OUT DBB,A". If P24 is set to a zero, KIRQ is forced low ...
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... MEMORY CONFIGURATIONS The FDC37B78x provides 2K of on-chip ROM and 256 bytes of on-chip RAM. Register Definitions Host I/F Data Register The Input Data and Output Data registers are each 8 bits wide. A write to this 8 bit register will load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled ...
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... POR) and externally generated reset signals. In powerdown mode, the external clock signal is not loaded by the chip. DEFAULT RESET CONDITIONS The FDC37B78x has one source of reset: an this bit is external reset via the RESET_DRV pin. Refer to TABLE 60 for the effect of each type of reset on the internal registers ...
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... GATEA20 AND KEYBOARD RESET The FDC37B78x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. Bit Function 7:6 Reserved. Returns 00 when read 5 Reserved. Returns a 1 when read 4 Reserved. Returns a 0 when read 3 Reserved ...
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Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of ...
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P20 KRST_GA20 P92 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command ...
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RTC INTERFACE The ISA interface is functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus, the nIOR, nIOW and the Status Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN ISA ADDRESS* 0x70 (R/W) ...
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When RESET_DRV is active and the battery voltage is below 1-volt nominal, the following occurs: 1. Registers 00-0D are initialized to 00h. 2. Access to all registers from the host are blocked. RTC Interrupt The interrupt generated by the RTC ...
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Table 63 shows Bank 1, the second bank of CMOS registers which contains an additional 128 bytes of general purpose CMOS registers. Table 63 - Real Time Clock Address Map, Bank 1 ADDRESS REGISTER TYPE 0-7F R/W Note: CMOS Bank ...
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Table 64 - Time, Calendar and Alarm Bytes ADD REGISTER FUNCTION 0h Register 0: Seconds 1h Register 1: Seconds Alarm 2h Register 2: Minutes 3h Register 3: Minutes Alarm 4h Register 4: Hours (12 hour mode) (24 hour mode) 5h ...
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The UIP (update in progress) status bit is set during the interval. When the UIP bit goes high, the update cycle will begin 244 s later. Therefore low is read INPUT CLOCK FREQUENCY ...
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OSCILLATOR FREQUENCY DV2 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz 32.768 KHz Table 67 - Periodic Interrupt Rates RATE SELECT RS3 RS2 RS1 ...
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PIE The periodic interrupt enable bit is a read/write bit which allows the periodic-interrupt flag (PF) bit in Register C to cause the IRQB port to be driven low. The program writes a "1" to the PIE bit in order ...
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PF is set to a "1" independent of the state of the PIE bit. PF being a "1" sets the IRQF bit and initiates an IRQB signal when PIE is also a "1". The PF bit is cleared by RESET_DRV ...
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BIT 0 - AL_REM_EN One of the two control bits for the alarm wakeup function the “remember” enable bit for the second alarm. This bit, if set to 1, wil cause the system to power-up upon return of ...
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The IRQF bit in Register "1" whenever the IRQB port is being driven low. Frequency Divider The RTC has 22 binary divider stages following the clock input. The output of the divider signal ...
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SOFT POWER MANAGEMENT This chip employs soft power management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. This technique allows for software control over powerdown and ...
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FIGURE 3 - SOFT POWER MANAGEMENT FUNCTIONAL DIAGRAM OFF_EN OFF_DLY Button L Button Input ED; PG SP1 ED; L EN1 nSPOFF1 SPx ED; L ENx nSPOFF1 PWRBTNOR_EN A transition on the Button input any enabled A low pulse ...
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REGISTERS The following registers can be accessed when in configuration mode at Logical Registers B0-B3, B8 and F4, and when not in configuration they can be accessed through the Index and Data Register. All soft power management configuration registers are ...
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Figure 11 shows the soft power management logic with the override timer path from the button input. The override timer counts while the button is held (in the present implementation this would be when the button input is high) and ...
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... ACPI/PME/SMI FEATURES ACPI Features The FDC37B78x supports ACPI as described in this section. These features comply with the ACPI Specification, Revision 1.0. Legacy/ACPI Select Capability This capability consists of an SMI/SCI switch which is required in a system that supports both legacy and ACPI power management models. ...
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... SMI Events can also generate an SCI. See the SCI/PME and SMI/PME logic diagrams below. Device Sleep States Each device in the FDC37B78x supports two device sleep states, D0 (on) and D3 (off). The D3 state corresponds to the PCI defined D3cold state. With all devices off, the part is powered ...
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... PME Wake sources. PME_STS will become asserted independent of the state of the global PME enable, PME_EN. In the FDC37B78x the nPME pin is an open drain, active low, driver. The FDC37B78x nPME pin is fully isolated from other external devices that might pull the PCI nPME signal low; i.e., the ...
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ACPI/PME/SMI REGISTERS Logical Device A in the configuration section contains the address pointer to the ACPI power management register block, and PM1_BLK. These are run-time registers; Included in the PM1_BLK is an enable bit to allow the SCI group interrupt ...
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Register Block The registers in this block are powered by VTR and battery backed up. TABLE 68 - PM1/GPE REGISTER BLOCK Register PM1_STS 1 PM1_STS 2 PM1_EN 1 PM1_EN 2 PM1_CNTRL 1 PM1_CNTRL 2 Reserved Reserved GPE_STS 1 GPE_EN 1 ...
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... ACPI REGISTERS In the FDC37B78x, the PME wakeup events can be enabled as SCI events through the SCI_STS1 and SCI_EN1 bits in the GPE status and enable registers. See PME Interface and SMI/PME/SCI logic sections. Power Management 1 Status Register 1 (PM1_STS 1) Register Location: <PM1_BLK> System I/O Space ...
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BIT NAME 3 PWRBTNOR_STS This bit is set when the power switch over-ride function is set: If PWRBTNOR_EN is set, and if the Button_In signal is held asserted for more than four seconds. Hardware is also required to reset the ...
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... This 3-bit field defines the type of hardware sleep state the system enters when the SLP_EN bit is set to one. When this field is 000 the FDC37B78x will transition the machine to the off state when the SLP_EN bit is set to one. That is, with this field set to 000, nPowerOn will go inactive (float) after a 1-2 RTC clock delay when SLP_EN is set ...
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General Purpose Event Status Register 1 (GPE_STS1) Register Location: <PM1_BLK>+8 System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write (Note 0) Size: 8-bits BIT NAME 0 SCI_STS1 This bit is set when the device power management events (PME ...
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... The PME_Status bit is set when the FDC37B78x would normally assert the PCI nPME signal, independent of the state of the PME_En bit. Only active transitions on the PME Wake sources can set the PME_Status bit. The PME_Status bit is read/write-clear. Writing a “1” to the PME_Status bit will clear it (if there are no pending PME events) and cause the FDC37C78X to stop asserting the nPME, if enabled ...
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... PCI nPME signal. SMI Registers The FDC37B78x implements a group nSMI output pin. The nSMI group interrupt output consists of the enabled interrupts from each of the functional blocks in the chip plus other SMI events. The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 and 2 ...
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SMI Status Register 1 (SMI_STS1) Register Location: <PM1_BLK>+12h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Status Register 1 This register is used to read the status of the SMI inputs. Default = ...
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SMI Enable Register 1 (SMI_EN1) Register Location: < PM1_BLK >+14h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable Register This register is used to enable the different interrupt sources onto the 1 ...
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SMI Enable Register 2 (SMI_EN2) Register Location: < PM1_BLK >+15h System I/O Space Default Value: 00h on Vbat POR Attribute: Read/Write Size: 8-bits NAME SMI Enable This register is used to enable the different interrupt sources onto the Register 2 ...
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EITHER EDGE TRIGGERED INTERRUPTS Four GPIO pins are implemented that allow an interrupt to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. The either edge ...
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SMI/PME/SCI Logic The logic for the SMI, PME and SCI signals is shown in the figures that follow. MUX nPME nPME 0 0 nSCI pin 0 1 IRQ9 1 0 PME_STS Bit[6] Bits[6:5] Bit[5] of IRQ Mux Control Register PME_EN ...
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FIGURE 6 - SMI/PME LOGIC Group SMI nSMI out to pin EN_SMI or Serial Bit 7 IRQ2 of SMI_EN2 Register DEV_INT to nPME Interface EN_SMI_PME Logic Bit 6 of SMI_EN2 Register SMI_EN SMI_STS Registers Registers SMI_STS1 Register SMI_EN1 Register RING ...
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... POST. SYSTEM ELEMENTS Primary Configuration Address Decoder After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37B78x is in the Run Mode with all logical devices disabled. The logical devices may be configured through two standard Configuration I/O Ports (INDEX and ...
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Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Config Key = < 0x55> When in configuration mode, all logical devices function properly. Entering configuration mode has ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,3F0H MOV AX,055H CLI ; disable interrupts OUT DX,AL STI ; enable interrupts ;-------------------------------. ; CONFIGURE REGISTER ...
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CONFIGURATION REGISTERS HARD INDEX TYPE RESET GLOBAL CONFIGURATION REGISTERS 0x02 W 0x00 0x03 R/W 0x03 0x07 R/W 0x00 0x20 R 0x44 0x21 R 0x00 (Note 0) 0x22 R/W 0x00 0x23 R/W 0x00 0x24 R/W 0x04 Sysopt=0: 0x26 R/W 0xF0 Sysopt=1: ...
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HARD INDEX TYPE RESET Vcc POR LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0x74 R/W 0x04 0xF0 R/W 0x3C 0xF1 R/W 0x00 LOGICAL DEVICE 4 CONFIGURATION REGISTERS (Serial Port ...
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HARD INDEX TYPE RESET Vcc POR 0x72 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x30 R/W 0x00 0xB0 R/W - 0xB1 R/W - 0xB2 R 0xB3 R/W 0xB8 R/W - 0xC0 R/W - ...
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HARD INDEX TYPE RESET Vcc POR 0xE1 R/W - 0xE2 R/W - 0xE3 R/W - 0xE4 R/W - 0xE5 R/W - 0xE6 R/W - 0xE7 R/W - 0xEF R/W - 0xF0 R/W - 0xF1 R/W 0x00 0xF2 R/W 0x00 0xF3 ...
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Chip Level (Global) Control/Configuration Registers [0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero ...
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REGISTER ADDRESS Card Level 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Reserved Device ID 0x20 R A identification. Bits[7:0] = 0x44 when read Hard wired = 0x44 Device Rev 0x21 R A read only register which ...
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REGISTER ADDRESS OSC 0x24 R/W Bit[0] Reserved Bit [1] PLL Control Default = 0x04 PLL is on (backward Compatible) on Vcc POR PLL is off Reset_Drv Bits[3:2] OSC hardware = 01 Osc is on, BRG ...
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REGISTER ADDRESS TEST 3 0x2F R/W Default = 0x00, on Vcc POR or Reset_Drv hardware signal. Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are used. There is no ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports eight logical units and has eight sets of logical device registers. The eight logical devices are Floppy, Parallel Port, Serial ...
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LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,072) Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) DMA Channel (0x74,0x75) Select Default = 0x04 on Vcc POR or Reset_Drv 32-Bit Memory ...
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I/O Base Address Configuration Register TABLE 73 - I/O BASE ADDRESS CONFIGURATION REGISTER DESCRIPTION LOGICAL DEVICE LOGICAL REGISTER INDEX NUMBER DEVICE 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 ...
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LOGICAL DEVICE LOGICAL REGISTER INDEX NUMBER DEVICE 0x62,0x63 0x06 RTC n/a 0x62, 0x63 0x07 KYBD n/a 0x0A ACPI 0x60,0x61 Note 3:This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. BASE I/O ...
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Interrupt Select Configuration Register TABLE 74 - INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX Interrupt 0x70 (R/W) Request Level Select 0 Default = 0x00 on Vcc POR or Reset_Drv Note the responsibility of the software to ensure ...
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DMA Channel Select Configuration Register TABLE 75 - DMA CHANNEL SELECT CONFIGURATION REGISTER DESCRIPTION NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 on Vcc POR or Reset_Drv Note: A DMA channel is activated by setting the DMA ...
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ECP Mode: i) (DMA) dmaEn from ecr register. See table. ii) IRQ - See table. MODE (FROM ECR REGISTER) 000 PRINTER 001 010 011 100 101 110 111 CONFIG 5) Real Time Clock and Keyboard Controller: Refer to the ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc POR or VTR POR or VBAT POR (as shown) or the RESET_DRV signal. These registers ...
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... Bits[5:4] Reserved (could be used to store Floppy Drive Default = 0xFF C type) Bits[7:6] Reserved (could be used to store Floppy Drive on Vcc POR D type) or Reset_Drv Note: The FDC37B78x supports two floppy drives 0xF3 R Reserved, Read as 0 (read only) FDD0 0xF4 R/W Bits[1:0] Drive Type Select: DT1, DT0 Bits[2] ...
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Parallel Port, Logical Device 3 TABLE 77 - PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03] NAME REG INDEX PP Mode 0xF0 R/W Bits[2:0] Parallel Port Mode Register = 100 Printer Mode (default) = 000 Standard and Bi-directional ...
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Serial Port 1, Logical Device 4 TABLE 78 - SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: ...
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TABLE 79 - UART INTERRUPT OPERATION UART1 UART1 UART1 UART2 OUT2 bit IRQ State OUT2 bit This part of the table is based on the assumption that both UARTS have selected different IRQ pins asserted 0 ...
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Serial Port 2, Logical Device 5 TABLE 80 - SERIAL PORT 2, LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05] NAME REG INDEX Serial Port 2 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv IR Option ...
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RTC, Logical Device 6 TABLE 81 - RTC, LOGICAL DEVICE 6 [LOGICAL DEVICE NUMBER = 0X06] NAME REG INDEX RTC Mode Register 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv Note 1: The secondary base address must be ...
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KYBD, Logical Device 7 TABLE 82 - KYBD, LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07] NAME REG INDEX KRST_GA20 Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF DEFINITION 0xF0 KRESET and GateA20 Select R/W Bit[7] Polarity ...
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Auxiliary I/O, Logical Device 8 TABLE 83 - AUXILLIARY I/O, LOGICAL DEVICE 8 [LOGICAL DEVICE NUMBER = 0X08] NAME REG INDEX Soft Power Enable 0xB0 R/W Register 1 Default = 0x00 on Vbat POR DEFINITION The following bits are the ...
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NAME REG INDEX Soft Power Enable 0xB1 R/W Register 2 Default = 0x80 on Vbat POR DEFINITION The following bits are the enables for the wake-up function of the nPowerOn bit. When enabled, these bits allow their corresponding function to ...
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NAME REG INDEX Soft Power Status 0xB2 R/W Register 1 Default = 0x00 on Vbat POR DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused ...
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NAME REG INDEX Soft Power Status 0xB3 R/W Register 2 Default = 0x00 on Vbat POR DEFINITION The following bits are the status for the wake-up function of the nPowerOn bit. These indicate which of the enabled wakeup functions caused ...
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NAME REG INDEX Delay 2 Time Set 0xB8 R/W Register Default = 0x00 on VTR POR DEFINITION This register is used to set Delay 2 (for Soft Power Management value from 500 msec to 32 sec. The default ...
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NAME REG INDEX IRQ Mux Control 0XC0 R/W Register Default = 0x00 on Vbat POR DEFINITION This register is used to configure the IRQs, including PME, SCI and SMI. Bit[0] Serial/Parallel IRQs 0=Serial IRQs are used 1=Parallel IRQS are used ...