AT89C5131-PLTIL ATMEL Corporation, AT89C5131-PLTIL Datasheet - Page 101

• Manufacturer Part Number: AT89C5131-PLTIL
• Description: 8-bit Flash Microcontroller with Full Speed USB Device
• Manufacturer: ATMEL Corporation

Master Transmitter Mode
Master Receiver Mode
4136B–USB–09/03
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
In Figure 49 to Figure 52, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in SSCS. At these points, a ser-
vice routine must be executed to continue or complete the serial transfer. These service
routines are not critical since the serial transfer is suspended until the serial interrupt
flag is cleared by software.
When the serial interrupt routine is entered, the status code in SSCS is used to branch
to the appropriate service routine. For each status code, the required software action
and details of the following serial transfer are given in Table 85 to Table 86.
In the master transmitter mode, a number of data bytes are transmitted to a slave
receiver (Figure 49). Before the master transmitter mode can be entered, SSCON must
be initialised as follows:
CR0, CR1 and CR2 define the internal serial bit rate if external bit rate generator is not
used. SSIE must be set to enable SSLC. STA, STO and SI must be cleared.
The master transmitter mode may now be entered by setting the STA bit. The TWI logic
will now test the TWI bus and generate a START condition as soon as the bus becomes
free. When a START condition is transmitted, the serial interrupt flag (SI bit in SSCON)
is set, and the status code in SSCS will be 08h. This status must be used to vector to an
interrupt routine that loads SSDAT with the slave address and the data direction bit
(SLA+W).
When the slave address and the direction bit have been transmitted and an acknowl-
edgement bit has been received, SI is set again and a number of status code in SSCS
are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if
the slave mode was enabled (AA=logic 1). The appropriate action to be taken for each
of these status code is detailed in Table 84. This scheme is repeated until a STOP con-
dition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 84. After a repeated START condition (state 10h) SSLC may switch to the master
receiver mode by loading SSDAT with SLA+R.
In the master receiver mode, a number of data bytes are received from a slave transmit-
ter (Figure 50). The transfer is initialized as in the master transmitter mode. When the
START condition has been transmitted, the interrupt routine must load SSDAT with the
7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must
then be cleared before the serial transfer can continue.
When the slave address and the direction bit have been transmitted and an acknowl-
edgement bit has been received, the serial interrupt flag is set again and a number of
status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and
also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate
action to be taken for each of these status code is detailed in Table . This scheme is
repeated until a STOP condition is transmitted.
bit rate
CR2
SSIE
1
STA
0
STO
0
SI
0
AA
X
AT89C5131
bit rate
CR1
bit rate
CR0
101