AT89C51RC-33AC ATMEL Corporation, AT89C51RC-33AC Datasheet

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AT89C51RC-33AC

Manufacturer Part Number
AT89C51RC-33AC
Description
8-bit Microcontroller with 32K Bytes Flash
Manufacturer
ATMEL Corporation
Datasheet
Features
Description
The AT89C51RC is a low-power, high-performance CMOS 8-bit microcontroller with
32K bytes of Flash programmable read only memory and 512 bytes of RAM. The
device is manufactured using Atmel’s high-density nonvolatile memory technology and
is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout.
The on-chip Flash allows the program memory to be user programmed by a conven-
tional nonvolatile memory programmer. A total of 512 bytes of internal RAM are
available in the AT89C51RC. The 256-byte expanded internal RAM is accessed via
MOVX instructions after clearing bit 1 in the SFR located at address 8EH. The other
256-byte RAM segment is accessed the same way as the Atmel AT89-series and
other 8052-compatible products. By combining a versatile 8-bit CPU with Flash on a
monolithic chip, the Atmel AT89C51RC is a powerful microcomputer which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89C51RC provides the following standard features: 32K bytes of Flash, 512
bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89C51RC is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.
Compatible with MCS-51
32K Bytes of Reprogrammable Flash Memory
Endurance: 1000 Write/Erase Cycles
4V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
512 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Hardware Watchdog Timer
Dual Data Pointer
Power-off Flag
®
Products
8-bit
Microcontroller
with 32K Bytes
Flash
AT89C51RC
Rev. 1920B–MICRO–11/02
1

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AT89C51RC-33AC Summary of contents

Page 1

... RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C51RC is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning ...

Page 2

... Pin Configurations AT89C51RC 2 TQFP P1 P0.4 (AD4) P1 P0.5 (AD5) P1 P0.6 (AD6) 30 P0.7 (AD7) RST 4 (RXD) P3 EA/VPP ALE/PROG (TXD) P3.1 7 (INT0) P3 PSEN (INT1) P3 P2.7 (A15) 24 P2.6 (A14) (T0) P3.4 10 (T1) P3 P2.5 (A13) PDIP (T2) P1 VCC (T2EX) P1 P0.0 (AD0) P1 P0.1 (AD1) P1 P0.2 (AD2) P1 P0.3 (AD3) P1 ...

Page 3

... PORT 0 DRIVERS PORT 0 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW INSTRUCTION REGISTER PORT 1 LATCH WATCH DOG PORT 1 DRIVERS P1.0 - P1.7 AT89C51RC P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PORT 3 ...

Page 4

... As inputs, Port 3 pins that are exter- nally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89C51RC, as shown in the following table. ) because of the internal pull-ups. ...

Page 5

... Program Store Enable is the read strobe to external program memory. When the AT89C51RC is executing code from external program memory, PSEN is acti- vated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...

Page 6

... Table 1. AT89C51RC SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 T2CON T2MOD 0C8H 00000000 XXXXXX00 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON TMOD ...

Page 7

... RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode. Interrupt Registers: The individual interrupt enable bits are in the IE register. Two pri- orities can be set for each of the six interrupt sources in the IP register. RCLK TCLK EXEN2 AT89C51RC Reset Value = 0000 0000B TR2 C/T2 CP/RL2 ...

Page 8

... Reset pin is input only WDIDLE Disable/Enable WDT in IDLE mode WDIDLE Operating Mode 0 WDT continues to count in IDLE mode 1 WDT halts counting in IDLE mode AT89C51RC 8 – – WDIDLE Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H ...

Page 9

... FFFFH are to external memory. The AT89C51RC has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes special function regis- ter (SFR) and 256 bytes expanded RAM (ERAM) ...

Page 10

... AT89C51RC 10 accesses the SFR at location 0S0H (which is P2). Instructions that use indirect address- ing access the Upper 128 bytes of data RAM. For example: MOV@R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space ...

Page 11

... WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89C51RC while in IDLE mode, the user should always set up a timer that will period- ically exit IDLE, service the WDT, and reenter IDLE mode. ...

Page 12

... Down Counter) AT89C51RC 12 Timer 0 and Timer 1 in the AT89C51RC operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. Timer 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). ...

Page 13

... RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt. AT89C51RC TH2 TL2 TF2 ...

Page 14

... Not Bit Addressable – – Bit 7 6 Symbol Function – Not implemented, reserved for future T2OE Timer 2 Output Enable bit DCEN When set, this bit allows Timer configured as an up/down counter AT89C51RC 14 C/ CONTR OL TR2 C/ RELO AD RCAP2H CONTROL EXEN2 – – – 5 ...

Page 15

... COUNTING RELOAD VALUE) 0FFH TH2 CONTROL TR2 RCAP2H (UP COUNTING RELOAD VALUE) C/ TH2 CONTROL TR2 C/ RCAP2H EXF2 CONTROL EXEN2 AT89C51RC TOGGLE 0FFH OVERFLOW TL2 INTERRUPT RCAP2L COUNT DIRECTION 1=UP 0=DO T2EX PIN TIMER 1 OVERFLOW ÷ 2 "0" "1" "1" ...

Page 16

... Baud Rate Generator AT89C51RC 16 Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 5 ...

Page 17

... Figure 6. Timer 2 in Clock-Out Mode OSC P1.0 (T2) TRANSITION DETECTOR P1.1 (T2EX) 1920B–MICRO–11/02 2 TR2 C/T2 BIT EXF2 EXEN2 AT89C51RC TL2 TH2 (8-BITS) (8-BITS) RCAP2L RCAP2H 2 T2OE (T2MOD.1) TIMER 2 INTERRUPT 17 ...

Page 18

... RCAP2H and RCAP2L. The AT89C51RC has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 7 ...

Page 19

... Figure 7. Interrupt Sources 0 INT0 1 TF0 0 INT1 1 TF1 TI RI TF2 EXF2 AT89C51RC (LSB) ES ET1 EX1 ET0 Function Disables all interrupts interrupt is acknowledged each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. ...

Page 20

... Oscillator Characteristics Idle Mode Power-down Mode AT89C51RC 20 XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 8. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 9 ...

Page 21

... ALE PSEN The AT89C51RC has three lock bits that can be left unprogrammed (U) or can be pro- grammed (P) to obtain the additional features listed in the following table. Table 7. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 ...

Page 22

... Chip Erase Sequence: Before the AT89C51RC can be reprogrammed, a Chip Erase operation needs to be performed. To erase the contents of the AT89C51RC, follow this sequence: 1. Raise ...

Page 23

... (3) L 12V AT89C51RC P3.4 P0.7-0 P3.3 P3.6 P3.7 Data A14 A14 OUT P0. P0. ...

Page 24

... A14 (P3.4) is not the same as the external memory address line A14 (P2.6). 4.5V to 5.5V AT89C51RC V P1 A13 PGM P2.0 - P2.5 P0 DATA P3.4 P2.6 P2.7 ALE PROG P3.3 P3.6 P3.7 XTAL2 RDY/ P3.0 BSY XTAL1 RST V IH GND PSEN 4.5V to 5.5V AT89C51RC V P1.0 - P1.7 CC PGM DATA A8 - A13 P0 P2.0 - P2.5 (USE 10K P3.4 PULL-UPS) P2.6 P2.7 ALE P3.3 P3 P3.7 XTAL XTAL1 RST IH GND PSEN 1920B–MICRO–11/02 ...

Page 25

... GLGH t Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float after ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC 1920B–MICRO–11/02 PP AT89C51RC Min Max Units 11.5 12 MHz 48t CLCL 48t CLCL 48t CLCL 48t ...

Page 26

... Flash Programming and Verification Waveforms P1.0 - P1.7 P2.0 - P2.5 P3.4 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) Lock Bit Programming Test Conditions Setup Lockbit_1 Data Setup ALE/PROG V = 6.5V CC AT89C51RC 26 PROGRAMMING ADDRESS DATA DVGL GHDX t AVGL t SHGL t GLGH EHSH t GHBL 100 µs VERIFICATION ADDRESS t AVQV DATA OUT ...

Page 27

... Parallel Chip Erase Mode Test Conditions Setup 200 ns ALE/PROG P3<0> Erase V = 6.5V CC 1920B–MICRO–11/02 Test Conditions Setup 200 ns DC Erase Erase 10 ms AT89C51RC DC Erase V = 4.5V to 5.5V CC Wait 10 ms before reprogramming 27 ...

Page 28

... exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89C51RC 28 Notice*: Stresses beyond those listed under “Absolute Maxi- = -40°C to 85°C and Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST) ...

Page 29

... Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. 12 MHz Oscillator Min 127 205 0 75 400 400 0 200 203 23 433 33 43 AT89C51RC Variable Oscillator Max Min Max -40 CLCL t -25 CLCL t -25 CLCL 233 4t -65 CLCL ...

Page 30

... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 External Data Memory Read Cycle ALE PSEN RD PORT FROM RI OR DPL PORT 2 AT89C51RC 30 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH ...

Page 31

... QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CC - 0.1V t CLCX Min AT89C51RC t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CLCL Max Units 33 MHz ...

Page 32

... Timing measurements are made at V (1) Float Waveforms V Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89C51RC 32 = 4.0V to 5.5V and Load Capacitance = 80 pF MHz Osc Min 1.0 ...

Page 33

... Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 1920B–MICRO–11/02 Ordering Code AT89C51RC-24AC AT89C51RC-24JC AT89C51RC-24PC AT89C51RC-24AI AT89C51RC-24JI AT89C51RC-24PI AT89C51RC-33AC AT89C51RC-33JC AT89C51RC-33PC Package Type AT89C51RC Package Operation Range 44A Commercial 44J (0°C to 70°C) ...

Page 34

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89C51RC TITLE 44A, 44-lead Body Size, 1 ...

Page 35

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1920B–MICRO–11/02 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89C51RC 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 4 ...

Page 36

... SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89C51RC 36 D PIN 0º ~ 15º REF ...

Page 37

... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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