24LC256 MicrochipTechnology, 24LC256 Datasheet - Page 9

• Manufacturer Part Number: 24LC256
• Description: 256KI2CCMOSSerialEEPROM
• Manufacturer: MicrochipTechnology

8.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types of
read operations: current address read, random read,
and sequential read.
8.1
The 24xx256 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
read access was to address n (n is any legal address),
the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24xx256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24xx256 discontinues transmission (Figure 8-1).
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
1998 Microchip Technology Inc.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = Don’t Care Bit
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
READ OPERATION
Current Address Read
S
S
T
A
R
T
1
CURRENT ADDRESS READ
RANDOM READ
SEQUENTIAL READ
0
S 1 0 1 0
S
T
A
R
T
CONTROL
1
BYTE
0 A A A 1
CONTROL
2 1 0
CONTROL
BYTE
BYTE
A A A
2 1 0
A
C
K
A
C
K
0
A
C
K
DATA n
X
BYTE
DATA
HIGH BYTE
ADDRESS
N
O
C
A
K
A
C
K
S
T
O
P
P
A
C
K
DATA n + 1
LOW BYTE
ADDRESS
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24xx256 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. Then, the master issues the
control byte again but with the R/W bit set to a one. The
24xx256 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24xx256 to discontinue transmission
(Figure 8-2). After a random read command, the
internal address counter will point to the address
location following the one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24xx256 transmits
the first data byte, the master issues an acknowledge
as opposed to the stop condition used in a random
read. This acknowledge directs the 24xx256 to transmit
the next sequentially addressed 8-bit word (Figure 8-
3). Following the final byte transmitted to the master,
the master will NOT generate an acknowledge but will
generate a stop condition. To provide sequential reads,
the 24xx256 contains an internal address pointer which
is incremented by one at the completion of each
operation. This address pointer allows the entire
memory contents to be serially read during one
operation. The internal address pointer will automati-
cally roll over from address 7FFF to address 0000 if the
master acknowledges the byte received from the array
address 7FFF.
A
C
K
24AA256/24LC256
Random Read
Sequential Read
A
C
K
DATA n + 2
S 1 0 1 0
S
T
A
R
T
CONTROL
BYTE
A A A
2 1 0
A
C
K
1
A
C
K
DATA n + X
BYTE
DATA
DS21203C-page 9
N
O
A
C
K
P
S
T
O
P
N
O
A
C
K
S
T
O
P
P