M58BW016BB

Manufacturer Part NumberM58BW016BB
Description16 Mbit 512Kb x32 / Boot Block / Burst 3V Supply Flash Memories
ManufacturerST Microelectronics
M58BW016BB datasheet
 
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PE4FEATURES SUMMARY
SUPPLY VOLTAGE
– V
= 2.7V to 3.6V for Program, Erase and
DD
Read
– V
= V
= 2.4V to 3.6V for I/O Buffers
DDQ
DDQIN
– V
= 12V for fast Program (optional)
PP
HIGH PERFORMANCE
– Access Time: 80, 90 and 100ns
– 56MHz Effective Zero Wait-State Burst Read
– Synchronous Burst Reads
– Asynchronous Page Reads
HARDWARE BLOCK PROTECTION
– WP pin Lock Program and Erase
SOFTWARE BLOCK PROTECTION
– Tuning Protection to Lock Program and
Erase with 64 bit User Programmable Pass-
word (M58BW016B version only)
OPTIMIZED for FDI DRIVERS
– Fast Program / Erase suspend latency
time < 6µs
– Common Flash Interface
MEMORY BLOCKS
– 8 Parameters Blocks (Top or Bottom)
– 31 Main Blocks
LOW POWER CONSUMPTION
– 5µA Typical Deep Power Down
– 60µA Typical Standby
– Automatic Standby after Asynchronous Read
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code M58BW016xT: 8836h
– Bottom Device Code M58BW016xB: 8835h
May 2003
M58BW016BT, M58BW016BB
M58BW016DT, M58BW016DB
16 Mbit (512Kb x32, Boot Block, Burst)
3V Supply Flash Memories
Figure 1. Packages
PQFP80 (T)
BGA
LBGA80 (ZA)
10 x 8 ball array
1/63

M58BW016BB Summary of contents

  • Page 1

    ... Automatic Standby after Asynchronous Read ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code M58BW016xT: 8836h – Bottom Device Code M58BW016xB: 8835h May 2003 M58BW016BT, M58BW016BB M58BW016DT, M58BW016DB 16 Mbit (512Kb x32, Boot Block, Burst) 3V Supply Flash Memories Figure 1. Packages PQFP80 (T) ...

  • Page 2

    ... Figure 3. LBGA Connections (Top view through package Figure 4. PQFP Connections (Top view through package Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Tuning Block Protection Table 2. Top Boot Block Addresses, M58BW016BT, M58BW016DT . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DB . . . . . . . . . . . . . . . . . . . 12 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Inputs (A0-A18 Data Inputs/Outputs (DQ0-DQ31 Chip Enable (E Output Enable (G) ...

  • Page 3

    ... Erase Status (Bit Program Status, Tuning Protection Unlock Status (Bit Status (Bit 3 Program Suspend Status (Bit Block Protection Status (Bit 1 Tuning Protection Status (Bit 0 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MAXIMUM RATING Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 3/63 ...

  • Page 4

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 14. Device Capacitance Table 15. DC Characteristics Figure 9. Asynchronous Bus Read AC Waveforms Table 16. Asynchronous Bus Read AC Characteristics Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 34 Table 17 ...

  • Page 5

    ... Figure 30. Command Interface and Program Erase Controller Flowchart ( Figure 31. Command Interface and Program Erase Controller Flowchart ( Figure 32. Command Interface and Program Erase Controller Flowchart ( Figure 33. Command Interface and Program Erase Controller Flowchart ( REVISION HISTORY Table 30. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 5/63 ...

  • Page 6

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB SUMMARY DESCRIPTION The M58BW016B 16Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Double- Word basis using a 2.7V to 3.6V V circuit and a V supply down to 2.4V for the In- DDQ put and Output buffers. Optionally a 12V V ...

  • Page 7

    ... Figure 2. Logic Diagram DDQ V DDQIN A0-A18 K L M58BW016BT E M58BW016BB RP M58BW016DT M58BW016DB SSQ M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 1. Signal Names A0-A18 DQ0-DQ7 V PP DQ8-DQ15 DQ16-DQ31 B DQ0-DQ31 DDQ V DDQIN V AI04155 SSQ ...

  • Page 8

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 3. LBGA Connections (Top view through package A15 A14 B A16 A13 C A17 A18 D DQ3 DQ0 E V DDQ DQ4 F V SSQ DQ7 G V DDQ DQ8 H DQ13 DQ12 J DQ15 DQ14 K V DDQIN RP 8/ A12 ...

  • Page 9

    ... V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 12 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 1 M58BW016BT M58BW016BB M58BW016DT M58BW016DB 64 DQ15 DQ14 DQ13 DQ12 V SSQ V DDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 53 DQ5 DQ4 V SSQ ...

  • Page 10

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Block Protection The M58BW016B features four different levels of block protection. The M58BW016D has the same block protection with the exception of the Tuning Block Protection, which is disabled in the factory. Write Protect Pin, WP, - When WP is low, V all the lockable parameter blocks (two upper (Top ) or lower (Bottom)) and all the main blocks are protected ...

  • Page 11

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB # 19 ( yes 17 yes ...

  • Page 12

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 3. Bottom Boot Block Addresses, M58BW016BB, M58BW016DB # Size (Kbit) Address Range 38 512 7C000h-7FFFFh 37 512 78000h-7BFFFh 36 512 74000h-77FFFh 35 512 70000h-73FFFh 34 512 6C000h-6FFFFh 33 512 68000h-6BFFFh 32 512 64000h-67FFFh 31 512 60000h-63FFFh 30 512 5C000h-5FFFFh 29 512 58000h-5BFFFh 28 512 54000h-57FFFh 27 512 50000h-53FFFh 26 512 4C000h-4FFFFh ...

  • Page 13

    ... Output Enable. When Output Disable, GD the outputs are high impedance independent- IL M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB ly of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. Write Enable (W). The Write Enable, W, input controls writing to the Command Interface, Input Address and Data latches ...

  • Page 14

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB ing Synchronous Burst Read operations. Bus sig- nals are latched on the active edge of the Clock. The Clock can be configured to have an active ris- ing or falling edge. In Synchronous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, V the rising edge of Latch Enable, whichever occurs first ...

  • Page 15

    ... Read AC Waveforms and Table 17, Asynchro- nous Latch Controlled Bus Read AC Characteris- tics for details on when the output becomes valid. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Note that, since the Latch Enable input is transpar- ent when set Low, V operations can be performed when the memory is ...

  • Page 16

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB the Address Inputs and pulsing Latch Enable Low The Address Inputs are latched by the Com- IL mand Interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and Input Data are latched on the rising edge of Chip Enable Write Enable, W, whichever occurs first ...

  • Page 17

    ... The second burst output is on the next clock valid edge after the Burst Address Advance B has been pulled Low. Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst Controller of the microprocessor needs to insert wait states. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB ...

  • Page 18

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 6. Synchronous Burst Read Bus Operations Bus Operation Address Latch Read Read Suspend Synchronous Burst Read Read Resume Burst Address Advance Read Abort, E Read Abort, RP Note Don't Care M15 = 0, Bit M15 is in the Burst Configuration Register. ...

  • Page 19

    ... Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Burst Type Bit (M7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’ ...

  • Page 20

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 7. Burst Configuration Register Bit Description M15 Read Select M14 (2) M13-M11 X-Latency M10 (3) M9 Y-Latency M8 Valid Data Ready M7 Burst Type M6 Valid Clock Edge M5-M4 M3 Wrapping M2-M0 Burst Length Note not allowed latencies can be calculated as the clock period). ...

  • Page 21

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB x4 x8 Sequential 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 – – – 0-1-2-3-4-5-6-7 – 1-2-3-4-5-6-7-8 – 2-3-4-5-6-7-8-9 – 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10- – 11 5-6-7-8-9-10-11- – 12 6-7-8-9-10-11- – 12-13 7-8-9-10-11-12- – ...

  • Page 22

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 5. Example Burst Configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 6. Example Burst Configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2-2 22/ VALID VALID VALID VALID NV NV=NOT VALID VALID VALID VALID VALID VALID VALID VALID ...

  • Page 23

    ... It is also possible during a Program or Erase operation, by disactivating the device with Chip Enable at V and then reactivating it with Chip En- IH M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB able and Output Enable The content of the Status Register may also be read at the completion of a Program, Erase or Suspend operation ...

  • Page 24

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB the command is issued then a fast erase operation will be executed, otherwise the operation will use goes below the during a fast erase the operation aborts, PPLK the Status Register V Status bit is set to ‘1’ and PP the command must be re-issued. ...

  • Page 25

    ... If the device is still locked a Read Memory Array command must be issued before re-issuing the Tuning Protection Unlock command. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Device locked means that the 64 bit password is wrong. If the unlock operation is attempted using a wrong code on an already unlocked device, the device becomes locked ...

  • Page 26

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Register bit 4 is set to '1' if there has been a pro- gram failure. Programming aborts if V drops out of the al- PP lowed range or RP goes Read Memory Array command must be issued to return the memory to read mode before issuing Table 9 ...

  • Page 27

    ... Parameter Block (64Kb) Program Main Block (512Kb) Program Parameter Block Erase Main Block Erase Program Suspend Latency Time Erase Suspend Latency Time Program/Erase Cycles (per Block) Note –40 to 125° 2.7V to 3.6V M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB M58BW016B/D Min Typ 0.030 0.23 ...

  • Page 28

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Tuning Protection operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Reg- ister command can be issued ...

  • Page 29

    ... Tuning Protection Status Note: 1. For the M58BW016D version the Tuning Protection Status bit is always set to ‘1’. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB When the Block Protection Status bit is set to ‘0’, no Program or Erase operations have been at- tempted to protected blocks since the last Clear Status Register command or hardware reset ...

  • Page 30

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB MAXIMUM RATING Stressing the device above the ratings listed in Ta- ble 12, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat the Operating sections of this specification is Table 12 ...

  • Page 31

    ... OUT Note 25° MHz A 2. Sampled only, not 100% tested. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB ment Conditions summarized in Table 13, Operating and AC Measurement Conditions. De- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. ...

  • Page 32

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Burst Read) DDB Supply Current (Standby) I DD1 Supply Current (Auto Low-Power) I Supply Current (Reset/Power-down) DD2 Supply Current (Program or Erase, ...

  • Page 33

    ... Output Enable High to Output Hi-Z GHQZ t Output Enable Low to Output Valid GLQV t Output Enable to Output Transition GLQX t Latch Enable Low to Chip Enable Low LLEL Note: 1. Output Enable G may be delayed M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB tAVAV tAVAV VALID VALID tAVQV tAVQV tLLEL tLLEL tELQX tELQX tELQV ...

  • Page 34

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 10. Asynchronous Latch Controlled Bus Read AC Waveforms A0-A18 tAVLL L tLHLL E G DQ0-DQ31 Table 17. Asynchronous Latch Controlled Bus Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Chip Enable High to Latch Enable Transition EHLX t Chip Enable High to Output Transition ...

  • Page 35

    ... DQ0-DQ31 Table 18. Asynchronous Page Read AC Characteristics Symbol Parameter t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX Note: For other timings see Table 16, Asynchronous Bus Read Characteristics. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB A0 and/or A1 tAVQV1 tAXQX OUTPUT Test Condition ...

  • Page 36

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 12. Asynchronous Write AC Waveform 36/63 ...

  • Page 37

    ... Figure 13. Asynchronous Latch Controlled Write AC Waveform M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 37/63 ...

  • Page 38

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL t Address Valid to Write Enable High AVWH t Data Input Valid to Write Enable High DVWH t Chip Enable Low to Latch Enable Low ELLL t Chip Enable Low to Write Enable Low ...

  • Page 39

    ... Figure 14. Synchronous Burst Read (Data Valid from ’n’ Clock Rising Edge) M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB 39/63 ...

  • Page 40

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 20. Synchronous Burst Read AC Characteristics Symbol Parameter t Address Valid to Latch Enable Low AVLL Burst Address Advance High to Valid Clock t BHKH Edge Burst Address Advance Low to Valid Clock t BLKH Edge t Chip Enable Low to Latch Enable low ELLL t Output Enable Low to Output Valid ...

  • Page 41

    ... R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge. Figure 17. Synchronous Burst Read - Burst Address Advance K ADD VALID L ADD G B M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB V tRLKH (2) The internal timing of R follows DQ. An external resistor, typically Q0 tGLQV tBLKH V V ...

  • Page 42

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 18. Reset, Power-Down and Power-up AC Waveform tVDHPH VDD, VDDQ Table 21. Reset, Power-Down and Power-up AC Characteristics Symbol t Reset/Power-down High to Chip Enable Low PHEL (1) Reset/Power-down High to Output Valid t PHQV t Reset/Power-down High to Write Enable Low PHWL t Reset/Power-down High to Output Enable Low ...

  • Page 43

    ... Typ A A1 0.400 A2 1.100 b 0.500 D 10.000 D1 7.000 ddd E 12.000 E1 9.000 e 1.000 FD 1.500 FE 1.500 SD 0.500 SE 0.500 M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB millimeters Min Max 1.700 0.350 0.450 – – – – – – 0.150 – – – – – – ...

  • Page 44

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 20. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Outline QFP-B Note: Drawing is not to scale. Table 23. PQFP80 - 80 lead Plastic Quad Flat Pack, Package Mechanical Data Symbol Typ 2.800 23.200 D1 20.000 D2 18.400 e 0.800 E 17.200 E1 14.000 E2 12.000 L 0 ...

  • Page 45

    ... Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de- vice, please contact the ST Sales Office nearest to you. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB M58BW016B =2 ...

  • Page 46

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB APPENDIX A. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...

  • Page 47

    ... Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV. 3. Not supported. Table 28. Device Geometry Definition Address A0-A18 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Data (1) V min, 2.7V 27h DD (1) V max, 3.6V 36h DD (2) V min B4h PP (2) ...

  • Page 48

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Table 29. Extended Query information Address Address offset A18-A0 (P)h 35h (P+1)h 36h (P+2)h 37h (P+3)h 38h (P+4)h 39h (P+5)h 3Ah (P+6)h 3Bh (P+7)h 3Ch (P+8)h 3Dh (P+9)h 3Eh (P+A)h 3Fh Note: 1. Not supported. 48/63 Data (Hex) 50h "P" 52h "R" Query ASCII string - Extended Table 49h "Y" ...

  • Page 49

    ... Read Status Register YES YES YES YES End Note error is found, the Status Register must be cleared before further P/E operations. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Invalid Error (1) NO Program Error (1) NO Program to Protect Block Error Program Command: – ...

  • Page 50

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 22. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block Write D0h Program Continues 50/ Program Complete Write FFh ...

  • Page 51

    ... Read Status Register YES YES b4 and YES YES End Note error is found, the Status Register must be cleared before further P/E operations. M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB NO Suspend YES NO Suspend Loop Invalid Error (1) YES Command Sequence Error NO Erase ...

  • Page 52

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 24. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program Write D0h Erase Continues 52/ Erase Complete Write FFh ...

  • Page 53

    ... Add: don't care Data: 0x78h Add: 0x00001h Data: Second 32 bit Read Status Register DEVICE LOCKED M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB TUNING PROTECTION UNLOCK SEQUENCE 1st: Write Cycle 2nd: Write Cycle (old code, factory setup = 0xFFFFh) YES 3rd: Write Cycle 4th: Write Cycle ...

  • Page 54

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 26. Unlock Device and Program a Tuning Protected Block Flowchart Reset Device locked by tuning code Add: don't care Data: 0x78h Add: 0x00000h Data: First 32 bit Add: don't care Data: 0xFFh Issue Read command Add: don't care Data: 0x78h ...

  • Page 55

    ... Add: don't care Data: 0x78h Add: 0x00001h Data: Second 32 bit Read Status Register DEVICE LOCKED M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB TUNING PROTECTION UNLOCK SEQUENCE 1st: Write Cycle 2nd: Write Cycle (First part of the tuning code) YES 3rd: Write Cycle 4th: Write Cycle ...

  • Page 56

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 28. Power-up Sequence to Burst the Flash Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read 56/63 BCR bit 15 = '1' Set Burst Configuration Register Command: – write 60h – write 03h and BCR on A15-A0 ...

  • Page 57

    ... Figure 29. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB NO YES NO 70h YES READ NO 20h STATUS YES ERASE SET-UP NO D0h YES A READ ...

  • Page 58

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 30. Command Interface and Program Erase Controller Flowchart ( 48h YES TP 78h PROGRAM SET_UP F TP UNLOCK SET_UP G 58/63 NO YES NO 60h YES NO FFh SET BCR SET_UP YES NO 03h YES D AI03836 ...

  • Page 59

    ... Figure 31. Command Interface and Program Erase Controller Flowchart (c) B READ STATUS READ ARRAY M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB NO ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES READY NO NO READ B0h STATUS YES ERASE SUSPEND ...

  • Page 60

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB Figure 32. Command Interface and Program Erase Controller Flowchart ( READ STATUS READ ARRAY 60/63 PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS C PROGRAM YES READY NO NO READ B0h STATUS YES PROGRAM SUSPEND YES READY NO READ STATUS ...

  • Page 61

    ... Figure 33. Command Interface and Program Erase Controller Flowchart (e) M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB PROGRAM YES NO READY UNLOCK YES NO READY READ STATUS READ STATUS AI03839 61/63 ...

  • Page 62

    ... M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB REVISION HISTORY Table 30. Document Revision History Date Version January-2001 -01 05-Jun-2001 -02 15-Jun-2001 -03 17-Jul-2001 -04 17-Dec-2001 -05 17-Jan-2002 -06 30-Aug-2002 6.1 4-Sep-2002 7.0 13-May-2003 7.1 62/63 Revision Details First Issue. Major rewrite and restructure. Nd and Ne values changed in PQFP80 Package Mechanical Table PQFP80 Package Outline Drawing and Mechanical Data Table updated ...

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    ... Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners ...