M58BW016BB ST Microelectronics, M58BW016BB Datasheet - Page 13

• Manufacturer Part Number: M58BW016BB
• Description: 16 Mbit 512Kb x32 / Boot Block / Burst 3V Supply Flash Memories
• Manufacturer: ST Microelectronics

SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A18). The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be low when selecting the ad-
dresses.
The address inputs are latched on the rising edge
of Latch Enable L or Burst Clock K, whichever oc-
curs first, in a read operation.The address inputs
are latched on the rising edge of Chip Enable,
Write Enable or Latch Enable, whichever occurs
first in a Write operation. The address latch is
transparent when Latch Enable is low, V
dress is internally latched in an Erase or Program
operation.
Data Inputs/Outputs (DQ0-DQ31). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, V
outputs data from the memory array, the Electron-
ic Signature, the CFI Information or the contents of
the Status Register. The data bus is high imped-
ance when the device is deselected with Chip En-
able at V
at V
Register content is output on DQ0-DQ7 and DQ8-
DQ31 are at V
Chip Enable (E). The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
V
consumption to the Standby level.
Output Enable (G). The Output Enable, G, gates
the outputs through the data output buffers during
a read operation, when Output Disable GD is at
V
are high impedance independently of Output Dis-
able.
Output Disable (GD). The Output Disable, GD,
deactivates the data output buffers. When Output
Disable, GD, is at V
the Output Enable. When Output Disable, GD, is at
V
IH
IH
IL
, the outputs are high impedance independent-
. When Output Enable G is at V
deselects the memory and reduces the power
IL
IL
or Reset/Power-Down at V
, and Output Disable is at V
IH
, Output Enable at V
IL
.
IH
, the outputs are driven by
IH
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
, Output Disable
IH,
IL
IH
. The Status
, the outputs
the data bus
IL
. The ad-
ly of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as
there is no internal pull-up resistor to drive the pin.
Write Enable (W). The Write Enable, W, input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP). The
Down, RP, is used to apply a hardware reset to the
memory. A hardware reset is achieved by holding
Reset/Power-Down Low, V
Writing is inhibited to protect data, the Command
Interface and the Program/Erase Controller are re-
set. The Status Register information is cleared and
power consumption is reduced to deep power-
down level. The device acts as deselected, that is
the data outputs are high impedance.
After Reset/Power-Down goes High, V
memory will be ready for Bus Read operations af-
ter a delay of t
t
If Reset/Power-Down goes low, V
Erase, a Program or a Tuning Protection Program
the operation is aborted, in a time of t
mum, and data is altered and may be corrupted.
During Power-up power should be applied simulta-
neously to V
When the supplies are stable RP is taken to V
Output Enable, G, Chip Enable, E, and Write En-
able, W, should be held at V
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
erase or program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
See Table 21 and Figure 18, Reset, Power-Down
and Power-up Characteristics, for more details.
Latch Enable (L). The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L, for Asynchronous Latch
Enable Controlled Read or Write or Synchronous
Burst Read operations. In Synchronous Burst
Read operations the address is latched on the ac-
tive edge of the Clock when Latch Enable is Low,
V
without affecting the address used by the memory.
When Latch Enable is Low, V
parent. Latch Enable, L, can remain at V
Asynchronous Random Read and Write opera-
tions.
Burst Clock (K). The Burst Clock, K, is used to
synchronize the memory with the external bus dur-
PHWL
IL
. Once latched, the addresses may change
.
DD
PHEL
and V
or Bus Write operations after
DDQ(IN)
IL
IH
, for at least t
IL
with RP held at V
during power-up.
, the latch is trans-
IL
, during a Block
Reset/Power-
PLRH
IH
maxi-
, the
PLPH
IL
13/63
for
IH
IL
.
.
.