PC28F640P30 Intel Corporation, PC28F640P30 Datasheet
PC28F640P30
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PC28F640P30 Summary of contents
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... Embedded Memory (P30) product is the latest generation of Intel ® StrataFlash memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device brings reliable, two-bit-per-cell storage technology to the embedded flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, and support for code and data storage ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation * Other names and brands may be claimed as the property of others. April 2005 ...
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... Power Up and Down ...........................................................................................................46 8.2 Reset Specifications ...........................................................................................................46 8.3 Power Supply Decoupling...................................................................................................47 9.0 Device Operations .................................................................................................................48 9.1 Bus Operations ...................................................................................................................48 9.1.1 Reads ....................................................................................................................48 9.1.2 Writes.....................................................................................................................49 9.1.3 Output Disable .......................................................................................................49 9.1.4 Standby..................................................................................................................49 9.1.5 Reset .....................................................................................................................49 9.2 Device Commands .............................................................................................................50 9.3 Command Definitions .........................................................................................................51 Datasheet Intel StrataFlash ..............................................................................................................9 ............................................................................................................10 ......................................................................................17 ...........................................................29 .....................................................................................................31 .....................................................................................46 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family April 2005 3 ...
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... Protection Registers ........................................................................................................... 72 13.3.1 Reading the Protection Registers .......................................................................... 73 13.3.2 Programming the Protection Registers.................................................................. 73 13.3.3 Locking the Protection Registers ........................................................................... 74 14.0 Special Read States 14.1 Read Status Register.......................................................................................................... 75 14.1.1 Clear Status Register............................................................................................. 76 14.2 Read Device Identifier ........................................................................................................ 76 April 2005 Intel StrataFlash 4 .................................................................................................. 61 ............................................................................................................. 75 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet ...
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... Flowcharts Appendix C Common Flash Interface Appendix D Additional Information Appendix E Ordering Information for Discrete Products Appendix F Ordering Information for SCSP Products Datasheet Intel StrataFlash ..........................................................................................78 ............................................................................................................85 ................................................................................93 ................................................................................... 100 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family ........................................ 101 ..............................................102 April 2005 5 ...
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... P30 Family Revision History Revision Date Revision April 2005 -001 April 2005 Intel StrataFlash 6 Initial Release ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Description Datasheet ...
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... Introduction This document provides information about the Intel StrataFlash® Embedded Memory (P30) device and describes its features, operation, and specifications. 1.1 Nomenclature Block : Main block : Parameter block : Top parameter device : Bottom parameter device : 1.2 Acronyms BEFP : CUI : MLC : OTP : PLR : PR : RCR : ...
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... Denotes one element of a signal group membership, such as an individual address bit. Binary unit Eight bits Two bytes, or sixteen bits 1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes 1,048,576 words ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet ...
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... This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device. The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. ...
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... A 0.050 - 1 A 0.965 0.995 2 b 0.100 0.150 c 0.100 0.150 D 18.200 18.400 1 E 13.800 14.000 e - 0.500 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 See Detail Seating Plane [231369-90] Inches Max Min Nom Max 1.200 - - 0.047 - 0.002 - - 1.025 ...
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... Sym Min Nom D 19.800 20.00 L 0.500 0.600 ∅ 0° 3° 0.150 0.250 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Inches Max Min Nom Max 20.200 0.780 0.787 0.795 0.700 0.020 0.024 0.028 - - 56 - 5° 0° ...
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... Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Note: Daisy Chain Evaluation Unit information is at Intel® Flash Memory Packaging Technology design/flash/packtech. April 2005 Intel StrataFlash ...
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... D 9.900 10.000 E 7.900 8.000 e - 0.800 1.100 1.200 0.500 0.600 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family raw ing not to scale. Inches Max Min Nom Max 1.200 - - 0.0472 - 0 ...
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... A2 - 0.740 b 0.300 0.350 D 10.900 11.00 E 7.900 8. 0. 1.100 1.200 S2 1.000 1.100 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 raw ing not to s cale . Inches Max Min Nom Max 1.000 - - 0.0394 - 0.0046 - - - - ...
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... D 10.900 11.000 E 7.900 8.000 e - 0.800 1.100 1.200 S2 1.000 1.100 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family raw ing not to scale . Inches Max Min Nom Max 1.200 - - 0.0472 - ...
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... 1.070 b 0.325 0.375 D 10.900 11.000 E 10.900 11.000 e - 0.800 2.600 2.700 S2 1.000 1.100 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Drawing not to scale. Inches Max Min Nom Max 1.400 - - 0.0551 - 0.0079 - - - - 0 ...
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... A24 is valid for 256-Mbit densities and above; otherwise connect (NC). Datasheet Intel StrataFlash Intel StrataFlash ® Embedded Memory (P 30) 56-Lead TSOP Pinout Top View ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family 56 WAIT ...
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... ADV# WAIT OE# OE# WAIT ADV# VCCQ DQ5 DQ6 DQ14 WE# WE# DQ14 DQ6 VSS DQ13 VSS DQ7 A24 A24 Easy BGA ® Embedded Memory (P30) Order Number: 306666, Revision: 001 A18 VCC A13 VPP A19 A25 ...
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... DQ3 DQ12 F1-OE# DQ9 DQ11 DQ4 RFU RFU RFU RFU VSS VCCQ VCC VSS DU Depop Depop Depop ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Depop VCC A21 A11 B CLK A22 A12 C RFU A9 A13 D E ...
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... Input down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V should not be attempted. Set V ...
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... WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through. FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When ...
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... Input down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function enabling blocks to be erased or programmed using software commands. Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when V should not be attempted. Set V ...
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... OE# WE# CLK ADV# Flash Die #2 (256-Mbit) A[MAX:0] QUAD+ 4-Die (1-Gbit) Device Configuration Flash Die #1 (256-Mbit) Flash Die #2 (256-Mbit) ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family RST# VCC VPP VCCQ VSS DQ[15:0] WAIT RST# VCC VPP VCCQ ...
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... P30 Family 4.4 Memory Maps Table 7 through Table 10 Operations” on page 61 Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region # (KB) 32 258 FFC000 - FFFFFF 32 255 FF0000 - FF3FFF 15 128 254 FE0000 - FEFFFF 128 240 F00000 - F0FFFF 128 239 ...
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... Table 7. Discrete Top Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region # (KB) 128 111 6F0000 - 6FFFFF 6 128 96 600000 - 60FFFF 128 95 5F0000 - 5FFFFF 5 128 80 500000 - 50FFFF 128 79 4F0000 - 4FFFFF 4 128 64 400000 - 40FFFF 128 63 3F0000 - 3FFFFF 3 128 48 300000 - 30FFFF 128 47 2F0000 - 2FFFFF ...
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... P30 Family Table 8. Discrete Bottom Parameter Memory Maps (all packages) Programming Size Blk 256-Mbit Region (KB) 128 210 CF0000 - CFFFFF 12 128 195 C00000 - C0FFFF 128 194 BF0000 - BFFFFF 11 128 179 B00000 - B0FFFF 128 178 AF0000 - AFFFFF 10 128 163 A0000 - A0FFFF 128 ...
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... Table 9. 512-Mbit Memory Map (Easy BGA and QUAD+ SCSP) Flash Die # Die Stack Config. 2 (Top Parameter) Flash Die #1 (Bottom 1 Note: Refer to 256-Mbit Memory Map Datasheet Intel StrataFlash Blk 128-Mbit 10 ...
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... P30 Family Table 10. 1-Gbit Memory Map (QUAD+ SCSP only) Flash Die # Die Stack Config. 4 (Top Parameter) 3 (Bottom Parameter) 2 (Top Parameter) 1 (Bottom Parameter) Note: Refer to 256-Mbit Memory Map April 2005 Intel StrataFlash 28 1-Gbit Flash (4x256-Mbit w/ 2CE) Size (KB) Blk 32 258 32 255 Flash Die #4 ...
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... 2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and V CC may overshoot to +11.5 V for periods < 20 ns. PP ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Maximum Rating Notes –40 °C to +85 °C –65 °C to +125 °C –0 +4.1 V – ...
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... In typical operation, the VPP program voltage is V hours. April 2005 Intel StrataFlash 30 Parameter CMOS inputs TTL inputs PPH = PPH PPH PPL ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Min Max Units –40 +85 °C 1.7 2.0 1.7 3.6 2.4 3.6 V 0.9 3.6 8.5 9 Hours 100,000 - - 1000 Cycles ...
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... Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Test Conditions Notes Max Max CCQ CCQ CCQ ...
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... V – 0.1 CCQ - 0 1.0 - 0.9 can overshoot 0.4 V for durations less. IH CCQ and V PPL ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Test Conditions program in progress PP PPL program in progress PP PPH erase in progress PP PPL erase in progress PP PPH, ...
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... CCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends CCQ Device Under Test R201 R202 R203 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family V /2 Output CCQ = Out (pF) ...
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... Silicon die capacitance only, add 1 pF for discrete packages. April 2005 Intel StrataFlash 34 Signals Min Typ Max ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Unit Condition Note Typ temp = 25 °C, pF Max temp = 85 °C, 1,2 1.95 V), CC CCQ Discrete silicon die ...
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... R302 t ADV# low setup to CLK VLCH/L R303 t CE# low setup to CLK ELCH/L R304 t CLK to output valid / t CHQV CLQV Datasheet Intel StrataFlash Parameter ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Min Max Unit Notes ...
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... ELQV GLQV whichever timing specification is satisfied first. CHAX VHAX Parameter Speed – 2.0 V Vcc = 1.8 V – 2.0 V Vcc = 1.7 V – 2.0 V Vcc = 1.8 V – 2.0 V Vcc = 1.7 V – 2.0 V Vcc = 1.8 V – 2.0 V Vcc = 1.7 V ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Min Max Unit Notes 1 1,4 1 ...
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... CE#’s falling edge without impact to t ELQV GLQV whichever timing specification is satisfied first. CHAX VHAX ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Min Max Unit Notes ...
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... OE# [G] R15 WAIT [T] Data [D/Q] Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low). April 2005 Intel StrataFlash ® Embedded Memory (P30) Order Number: 306666, Revision: 001 R8 R9 R17 R8 R9 R17 R10 Datasheet ...
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... WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either during or one data cycle before valid data. 2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by CE# deassertion after the first word in the burst. Datasheet ...
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... At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is not 4-word boundary aligned. April 2005 Intel StrataFlash 40 R307 R312 R304 R4 R305 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 R304 R304 R304 R305 R305 R305 Datasheet ...
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... WP# setup to WE# high BHWH Datasheet Intel StrataFlash y R307 R4 R304 R304 R305 Q0 Parameter setup to WE# high PP hold from Status read PP ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family R8 R9 R17 R10 Min Max Units Notes 150 - ns 1,2,3 ...
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... CE# or WE# high (whichever occurs first) to WHWL EHEL WHWL must be met when transitioning from a write cycle to a synchronous burst read ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Min Max Units Notes 1,2,9 1,2,3,6 ...
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... WAIT [T] Data [D/Q] W1 RST# [P] Datasheet Intel StrataFlash R15 R17 R10 W18 W14 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family R10 R15 R17 April 2005 43 ...
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... R307 R312 R304 R7 R305 Q R302 R301 W8 R306 R106 R104 R104 W6 R303 R11 R11 W18 W19 W20 W7 D ® Embedded Memory (P30) Order Number: 306666, Revision: 001 W5 W18 W6 W21 W21 W22 W22 W 8 W15 R15 R307 R304 ...
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... BEFP Setup n/a 32-KByte Parameter - 128-KByte Main - Program suspend - Erase suspend - = +25 °C and nominal voltages. Performance numbers are valid for all C ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family V V PPL PPH Units Notes Typ Max Min Typ Max ...
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... Reset Specifications Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected ...
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... RST# high 8.3 Power Supply Decoupling Flash memory devices require careful power supply de-coupling. Three basic power supply current considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks produced when CE# and OE# are asserted and deasserted. When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs’ ...
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... Reads To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on page 53 Section 14.0, “ ...
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... As with any automated device important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory the system boot device CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data ...
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... WA 2 Write BA 1 Write DBA 1 Write DBA 2 Write BA 2 Write BA 2 Write BA ® Embedded Memory (P30) Order Number: 306666, Revision: 001 50. Several commands are used to Second Bus Cycle (2) (1) Data Oper Addr Data 0xFF - - - 0x90 Read DBA + IA ID 0x98 Read DBA + QA ...
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... First command cycle address should be the same as the operation’s target address. DBA = Device Base Address (NOTE: needed for 2 or more die stacks Identification code address offset CFI Query address offset Word address of memory location to be written Address within the block. PRA = Protection Register address. LRA = Lock Register address. ...
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... The confirm command is Issued after the data streaming for writing into the buffer is done. This instructs the WSM to perform the Buffered Program algorithm, writing the data from the buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (BEFP) ...
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... Following a device power-up or reset, asynchronous page mode is the default read mode and the device is set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. ...
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... Falling edge 1 = Rising edge (default) Reserved bits should be cleared (0) ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Section 9.2, “Device 76). Burst CLK RES RES ...
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... No Wrap; Burst accesses do not wrap within burst length (default) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved) ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family for Latency Code Settings. April 2005 55 ...
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... Valid Valid Output Output Output Valid Valid Output Output Valid Output Latency Count Settings Frequency Support (MHz ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Valid Valid Valid Valid Output Output Output Output Valid Valid Valid Valid Output Output ...
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... WAIT is set to a deasserted state as determined by RCR[10]. See 17, “Asynchronous Single-Word Read (ADV# Latch)” on page Page-Mode Read Timing” on page Datasheet Intel StrataFlash Address Code 3 High-Z R103 39. ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family t Data 3 4 Data WAIT Figure 38, and Figure 18, “ ...
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... When DH is cleared, output data is held for one clock (see Figure 30). The processor’s data setup time and the flash memory’s clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: ...
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... Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family 16-Word Burst Continuous Burst (BL[2:0] = 0b011) (BL[2:0] = 0b111) 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… 4-5-6-7-8-9-10… 5-6-7-8-9-10-11… 14-15-16-17-18-19-20-… 15-16-17-18-19-20-21-… 0-1-2-3-4-5-6-… 1-2-3-4-5-6-7-… 2-3-4-5-6-7-8-… 3-4-5-6-7-8-9-… ...
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... The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 25, “ ...
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... Execute in Place (XIP) is defined as the ability to execute code directly from the flash memory. XIP applications must partition the memory such that code and data are in separate programming regions (see Table 26, “Programming Regions per Device” on page Region should contain only code or data, and not both. The following terms define the difference between code and data ...
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... Programming the flash memory array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to ones only by erasing the block (see 12.0, “Erase Operations” on page The Status Register can be examined for programming progress and errors by reading at any address ...
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... After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure ...
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... BEFP programs one block at a time; all buffer data must fall within a single block • BEFP cannot be suspended • Programming to the flash memory array can occur only when the buffer is full NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00 ...
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... The starting address for data entry must be buffer size aligned, if not the BEFP algorithm will be aborted and the program fails and (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array ...
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... PP PPH ≤ PPLK V VCC CC VPP • Low Voltage Programming Only • Full Device Protection Unavailable ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Section 7.5, 86). PP -level error. Block PP ; they may still be programmed and read, VCC CC VPP VCC VPP Datasheet ...
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... During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by programming the block (see The Status Register can be examined for block erase progress and errors by reading any address ...
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... Erase Protection When absolute hardware erase protection is provided for all device blocks below V , erase operations halt and SR[3] is set indicating a V PPLK April 2005 Intel StrataFlash 68 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 86 -level error. PP Datasheet ...
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... Block Locking Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased ...
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... Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock -Down (0x60/0x2F hardware control to this block. DQ1 = ‘1’, Lock-Down has been issued to this block. locked. Hardware Locked and Locked-Down states. ® Embedded Memory (P30) Order Number: 306666, Revision: 001 . Locked-down IL Figure 32, “Block Locking Section 14.2, Locked- ...
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... Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Appendix A, “Write State Machine” on blocks 3:0 (parameters) block 4 (main) block 5 (main) block 6 (main) ...
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... Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked. April 2005 Intel StrataFlash 72 Figure 33, “Protection Register Map” on page ® Embedded Memory (P30) Order Number: 306666, Revision: 001 73). Datasheet ...
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... Section 9.2, “Device Commands” on page shows the address offsets of the Protection Registers and Lock Registers. 50). Next, write the desired Protection Register data to the same Figure 33, “Protection Register Map” on page ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family 1 0 ...
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... Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked. April 2005 Intel StrataFlash 74 50). The physical addresses of the Lock Registers are ® Embedded Memory (P30) Order Number: 306666, Revision: 001 92). Issuing the 77). Datasheet ...
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... Name 0 = Device is busy; program or erase cycle in progress; SR[0] valid Device is ready; SR[6:1] are valid Erase suspend not in effect Erase suspend in effect. ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family , and block- PP Default Value = 0x80 Program Block- BEFP Suspend ...
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... WSM is not busy and buffer is available for loading Reserved for Future Use (RFU). for details on issuing the Read Device Identifier ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Default Value = 0x80 . The PP and Table 30, “Device ID codes” Datasheet ...
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... Item Address 0x00 0x01 BBA + 0x02 0x05 0x80 0x81–0x84 0x85–0x88 0x89 0x8A–0x109 Device Density 64-Mbit 128-Mbit 256-Mbit ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family (1) Data 0089h ID (see Table 30) Lock Bit 0b0 0b1 0 ...
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... BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 BP Busy BP Busy BP Suspend BP Busy Erase Busy Erase Erase Busy Suspend Erase Suspend Erase Erase Busy Suspend ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Clear Lock, Unlock, Read Read Status Lock-down, Status ID/Query (5) (4) Register CR setup ...
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... BP Suspend in Erase Suspend BP Busy in in Erase Suspend Erase Suspend Erase Suspend (Unlock Block) BEFP Loading Data (X=32) ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Clear Lock, Unlock, Read Read Status Lock-down, Status ID/Query (5) (4) Register CR setup (70H) ...
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... Data load into Ready Program Buffer is complete; ELSE BP Load 2 Ready (Error) (Proceed if Ready (Error) unlocked or lock error) BP Busy BP Suspend Ready (Error) Erase Busy Erase Suspend ® Embedded Memory (P30) Order Number: 306666, Revision: 001 WSM (1) Operation Completes N/A Ready N/A Ready N/A Ready N/A Ready N/A Datasheet ...
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... BP Suspend in Erase Suspend Erase Erase Suspend Suspend Erase Suspend (Lock Error) (Set CR) Block) Ready (BEFP Ready (Error) Loading Data) BEFP Busy Ready ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family WSM (1) Operation Completes NA Erase Suspend N/A N/A Erase Suspend N/A Ready ...
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... ULB Confirm Suspend (3, 4) Setup (8) (E8H) (20H) (30H) (D0H) (B0H) Status Read Status Read Status Read Output does not change. ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Clear Lock, Unlock, Read Read Status Lock-down, Status ID/Query (5) (4) Register CR setup (70H) ...
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... To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation ...
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... Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. 9. WA0 refers to the block address latched during the first write cycle of the current operation. April 2005 Intel StrataFlash 84 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Datasheet ...
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... If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register Device command clears the Status Register error bits. Protect Error ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Command Comments Program Data = 0x40 ...
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... Write If the suspended partition was placed in Read Array mode: Write Read Array Write FFh Pgm'd Partition Read Array Data ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Command Comments Program Data = B0h Suspend Addr = Block to suspend (BA) Read Data = 70h Status ...
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... Block Address Issue Read Buffer Program Aborted Status Register Command No 0=No Suspend Yes Program? SR[7] = 1=Yes ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Bus Command Comments Operation Buffer Prog. Data = 0xE8 Write Setup Addr = Word Address SR[7] = Valid Read ...
Page 88
... Last No = Fill buffer again Standby Data? Yes = Exit Exit Prog & Data = 0xFFFF @ address Write Verify Phase not in current block ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Exit Phase Read Status Reg. No (SR[7]=0) BEFP Exited? Yes (SR[7]=1) Full Status Check Procedure ...
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... Only the Clear Status Register command clears SR[ 5 error is detected, clear the Status register before Block Locked Error attempting an erase retry or other error recovery. ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Comments Block Data = 0x20 ...
Page 90
... Write Program No Write Loop Write Write 0xFF, (Read Array) Erased Partition Read Array Data ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Command Comments Read Data = 0x70 Status Addr = Any partition address Data = 0xB0 Erase Addr = Same partition address as Suspend above Status Register data ...
Page 91
... Status Idle None No Read Write Array (Read Array) ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Comments Data = 0x60 Addr = Block to lock/unlock/lock-down Data = 0x01 (Block Lock) 0xD0 (Block Unlock) 0x2F (Lock-Down Block) Addr = Block to lock/unlock/lock-down Data = 0x90 ...
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... Only the Clear Staus Register command clears SR[ error is detected, clear the Status register before Register Locked; attempting a program retry or other error recovery. Program Aborted ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Command Comments Program Data = 0xC0 PR Setup ...
Page 93
... Example of Query Structure Output of x16- Devices Datasheet Intel StrataFlash 50). System software can parse this database structure to obtain information Device ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Section 9.2, “Device ) only. The numerical offset value 7-0 ) and 00h in the high byte (DQ ...
Page 94
... AltVendor 00017h ID # 00018h ... ... Reserved for vendor-specific information Command set ID and vendor data offset Device timing & voltage information Flash device layout ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Byte Addressing: Hex Code Value D – "Q" 52 "R" ...
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... Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Hex Add. ...
Page 96
... Embedded Memory (P30) Order Number: 306666, Revision: 001 Code 27: See table below x32 x16 x8 28: -- — — — 29: --00 n 2A: --06 2B: --00 2C: See table below ...
Page 97
... BCD value in 100 mV bits 4–7 BCD value in volts optimum program/erase supply voltage PP bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts ® Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Hex Add. Code Value 10A --50 " ...
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... See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 ® Embedded Memory (P30) Order Number: 306666, Revision: 001 Hex Add. Code Value 118: --02 ...
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... Embedded Memory (P30) Order Number: 306666, Revision: 001 1-Gbit P30 Family Hex Add. Code ...
Page 100
... Flash Data Integrator (FDI) User’s Guide ® Intel Persistent Storage Manager User Guide Using Intel® Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode ® Migration Guide for Intel StrataFlash Memory (J3) to Intel StrataFlash Memory (P30) Application Note 812 ...
Page 101
... Intel® Flash Memory Device Density 640 = 64-Mbit 128 = 128-Mbit 256 = 256-Mbit Table 41. Valid Combinations for Discrete Products 64-Mbit TE28F640P30B85 TE28F640P30T85 JS28F640P30B85 JS28F640P30T85 RC28F640P30B85 RC28F640P30T85 PC28F640P30B85 PC28F640P30T85 Datasheet Intel StrataFlash ® Embedded Memory (P30 128-Mbit TE28F128P30B85 TE28F128P30T85 JS28F128P30B85 JS28F128P30T85 ...
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... RC = 64-Ball Easy BGA, leaded PC = 64-Ball Easy BGA, lead-free Group Designator 48F = Flash Memory only Flash Density die 2 = 64-Mbit 3 = 128-Mbit 4 = 256-Mbit Product Family P = Intel StrataFlash® Embedded Memory die Table 42. Valid Combinations for Stacked Products 64-Mbit 128-Mbit RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 ...