M5M5W816WG-10H Mitsubishi, M5M5W816WG-10H Datasheet
M5M5W816WG-10H
Related parts for M5M5W816WG-10H
M5M5W816WG-10H Summary of contents
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... The M5M5W816 is suitable for memory applications where a simple interfacing , battery operating and battery backup are the important design objectives. M5M5W816WG is packaged in a CSP (chip scale package), with the outline of 7.0mm x 8.5mm, ball matrix (48ball) and ball pitch of 0.75mm. It gives the best solution for a compaction of mounting area as well as flexibility of wiring pattern of printed circuit boards ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H FUNCTION The M5M5W816WG is organized as 524288-words by 16- bit. These devices operate on a single +1.8~2.7V power supply, and are directly TTL compatible to both input and output. Its fully static circuit needs no clocks and no refresh, and makes it useful. ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H ABSOLUTE MAXIMUM RATINGS Symbol Parameter V cc Supply voltage V Input voltage I V Output voltage O P Power dissipation d Operating T a temperature T Storage temperature stg DC ELECTRICAL CHARACTERISTICS Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H AC ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS Supply voltage Input pulse Input rise time and fall time Reference level Output loads (2) READ CYCLE Symbol t Read cycle time CR t (A) Address access time a t (S1) Chip select 1 access time a t (S2) ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H (4)TIMING DIAGRAMS Read cycle A 0~18 BC1,BC2 (Note3) S1 (Note3) S2 (Note3) OE (Note3 "H" level DQ 1~16 Write cycle ( W control mode ) A 0~18 BC1,BC2 (Note3) S1 (Note3) S2 (Note3 1~16 -85LI, 10LI, 85HI, 10HI 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM ( ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H Write cycle (BC control mode) A 0~18 BC1,BC2 S1 (Note3) S2 (Note3) (Note5) W (Note3) DQ 1~16 Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during S1 low, S2 high overlaps BC1 and/or BC2 low and W low. Note 5: When the falling edge simultaneously or prior to the falling edge of BC1 and/or BC2 or the falling edge rising edge of S2, the outputs are maintained in the high impedance state ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H Write cycle (S1 control mode) A 0~18 BC1,BC2 (Note3 (Note3) W (Note3) DQ 1~16 Write cycle (S2 control mode) A 0~18 BC1,BC2 (Note3 (Note3) W (Note3) DQ 1~16 -85LI, 10LI, 85HI, 10HI 8388608-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM (S1 (A) su (Note5) (Note4) ...
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... Ver. 0.1 M5M5W816WG -85L, 10L, 85H, 10H POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter Vcc Power down supply voltage (PD (BC) Byte control input BC1 & BC2 V I (S1) Chip select input (S2) Chip select input S2 Power down Icc (PD) supply current ...