VIPEr100ASP STMicroelectronics, VIPEr100ASP Datasheet - Page 14

• Manufacturer Part Number: VIPEr100ASP
• Description: SMPS PRIMARY I.C.
• Manufacturer: STMicroelectronics

Figure 16: Mixed Soft Start and Compensation
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer100/100A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (I
input voltage (V
G
The output impedance Z
amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain
A
A
where G
typically.
G
therefore A
impedance Z can be connected between the
COMP pin and ground in order to define more
accurately the transfer function F of the error
amplifier, according to the following equation, very
similar to the one above:
F
The error amplifier frequency response is reported
in figure 10 for different values of a simple
resistance connected on the COMP pin. The
unloaded transconductance error amplifier shows
an internal Z
impedance can be connected on the COMP pin to
Z
(S)
VOL
VOL
m
COMP
m
is well defined by specification, but Z
+ C3
= Gm x Z(S)
=
can be related to G
= G
----------------------- -
OSC
I
m
COMP
m
V
=
13V
VDD
value for VIPer100/100A is 1.5 mA/V
VOL
DD
x Z
COMP
-------------------------- -
V
+
-
I COMP
C4
COMP
are subject to large tolerances. An
COMP
DD
U1
VIPER100
COMP SOURCE
). Thus:
of about 330 K . More complex
C1
R1
DRAIN
=
COMP
m
COMP
-------- -
G
and Z
D1
1
m
+ C2
at the output of this
) versus change in
-------------------------- -
COMP
FC00131
V COMP
R3
R2
V
D2
D3
DD
:
COMP
AUXILIARY
WINDING
and
achieve different compensation laws. A capacitor
will provide an integrator function, thus eliminating
the DC static error, and a resistance in series
leads to a flat gain at higher frequency, insuring a
correct phase margin. This configuration is
illustrated on figure 18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
EXTERNAL CLOCK SYNCHRONIZATION:
The
capability, when connected to an external
frequency source. Figure 20 shows one possible
schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA through
the optotransistor.
PRIMARY PEAK CURRENT LIMITATION
The primary I
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit based
on Q1, R
Figure 17: Latched Shut Down
Shutdown
OSC
1
and R
R4
pin
VIPer100/SP - VIPer100A/ASP
DPEAK
Q2
R3
provides
2
clamps the voltage on the
current and, as resulting
R2
Q1
R1
OSC
a
13V
VDD
D1
synchronisation
+
-
VIPER100
U1
FC00110
COMP SOURCE
DRAIN
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