XC68HC705JJ7 Motorola, XC68HC705JJ7 Datasheet
XC68HC705JJ7
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XC68HC705JJ7 Summary of contents
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MC68HC705JJ7/D REV 4 MC68HC705JJ7 MC68HC705JP7 MC68HC705SJ7 MC68HC705SP7 MC68HRC705JJ7 MC68HRC705JP7 Advance Information HCMOS Microcontroller Unit ...
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...
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... Value change for clock — Value change for clock — Added Figure 15-10 and Figure 15-12 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Page Number(s) All All — Change label 94 — Change heading 96 179 188 189 225 226 213, 214, Figure 15-1 219, 223, and 227 MOTOROLA ...
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... Section 9. Simple Synchronous Serial Interface . . . . . 141 Section 10. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Section 11. Programmable Timer . . . . . . . . . . . . . . . . . 159 Section 12. Personality EPROM (PEPROM 175 Section 13. EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . 183 Section 14. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 191 Section 15. Electrical Specifications 209 MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA List of Sections List of Sections Advance Information 5 ...
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... List of Sections Section 16. Mechanical Specifications . . . . . . . . . . . . . 231 Section 17. Ordering Information . . . . . . . . . . . . . . . . . 237 Advance Information 6 MC68HC705JJ7 • MC68HC705JP7 — REV 4 List of Sections MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V and V Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . 30 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . 31 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PP PA0– ...
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... Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Condition Code Register .48 Arithmetic/Logic Unit (ALU .50 Section 4. Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IRQ/V Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 PP PA0–PA3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 IRQ Status and Control Register (ISCR MC68HC705JJ7 • MC68HC705JP7 — REV 4 Table of Contents MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Core Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . 60 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 61 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Timer Overflow Interrupt Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . .63 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 5. Resets Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Introduction ...
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... Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Data Direction Register Pulldown Register Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PB0, PBI, PB2, and PB3 Logic .93 PB4/AN4/TCMP/CMP1 Logic PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PB7/SCK Logic MC68HC705JJ7 • MC68HC705JP7 — REV 4 Table of Contents MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Port C (28-Pin Versions Only 101 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Direction Register 102 Port C Pulldown Devices . . . . . . . . . . . . . . . . . . . . . . . . . .103 Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Port Transitions .105 Section 8. Analog Subsystem Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Analog Status Register ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Timer Operation during Wait Mode 173 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Table of Contents MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 12. Personality EPROM (PEPROM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . 177 PEPROM Status and Control Register 178 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Section 13. EPROM/OTPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Introduction ...
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... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Operating Temperature Range 211 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Supply Current Characteristics (V = 4.5 to 5.5 Vdc 211 DD Supply Current Characteristics (V = 2.7 to 3.3 Vdc 212 DD DC Electrical Characteristics (5.0 Vdc 215 DC Electrical Characteristics (3.0 Vdc 216 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Table of Contents MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 = 5.0 Vdc 225 DD = 3.0 Vdc 226 DD Section 16. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 20-Pin Plastic Dual In-Line Package (Case 738 232 20-Pin Small Outline Integrated Circuit (Case 751D 233 28-Pin Plastic Dual In-Line Package (Case 710 233 28-Pin Small Outline Integrated Circuit (Case 751F) ...
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... Table of Contents Advance Information 16 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Table of Contents MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Title User Mode Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 User Mode Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 EPO Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory Map I/O Registers Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Vector Mapping .42 COP and Security Register (COPR 68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Accumulator ( Index Register (X Stack Pointer (SP .47 Program Counter (PC Condition Code Register (CCR) ...
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... Control (Mode 129 SIOP Block Diagram 142 SIOP Timing Diagram (CPHA = 143 SIOP Timing Diagram (CPHA = 144 SIOP Control Register (SCR 145 SIOP Status Register (SSR 148 SIOP Data Register (SDR 149 MC68HC705JJ7 • MC68HC705JP7 — REV 4 List of Figures Page MOTOROLA ...
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... Typical Run I 15-2 Typical Wait I 15-3 Typical Run I 15-4 Typical Wait I 15-5 Typical Stop I 15-6 Typical Temperature Diode Performance 219 15-7 Typical 500 kHz External Low-Power MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Title versus Internal DD Clock Frequency 213 versus Internal DD Clock Frequency 213 with External Oscillator . . . . . . . . . . . . . . . . . 214 DD with External Oscillator ...
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... Low-Voltage Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . 229 Advance Information 20 Title Oscillator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Frequency Range versus Resistance for High V Operating Range .223 Frequency Range versus Resistance for Low V Operating Range .223 MC68HC705JJ7 • MC68HC705JP7 — REV 4 List of Figures Page DD DD MOTOROLA ...
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... Core Timer Interrupt Rates and COP Timeout Selection . . . . 155 10-2 COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . . 157 11-1 Output Compare Initialization Example . . . . . . . . . . . . . . . . . 169 12-1 PEPROM Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Title Device Options by Part Number . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset/Interrupt Vector Addresses .52 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port B Pin Functions — ...
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... List of Tables Table 14-1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 195 14-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 196 14-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . 198 14-4 Bit Manipulation Instructions 199 14-5 Control Instructions 200 14-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Advance Information 22 Title MC68HC705JJ7 • MC68HC705JP7 — REV 4 List of Tables Page MOTOROLA ...
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... Introduction The Motorola MC68HC705JJ7 and MC68HC705JP7 are erasable programmable read-only memory (EPROM) versions of the MC68HC05JJ/JP Family of microcontrollers (MCU). MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 1. General Description Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V and V Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Crystal Oscillator ...
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... Software mask and request bit for IRQ interrupt with MOR selectable sensitivity on IRQ interrupt (edge- and level-sensitive or edge-only) On-chip oscillator with device option of crystal/ceramic resonator or resistor-capacitor (RC) operation and MOR selectable shunt resistor design MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description MOTOROLA ...
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... The exact values and their tolerance or limits are specified in Specifications security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA ...
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... Table 1-1 and to Section 17. Ordering Information Table 1-1. Device Options by Part Number Part Pin Oscillator Number Count 20 Crystal/resonator 28 Crystal/resonator 20 Crystal/resonator 28 Crystal/resonator 20 Resistor-capacitor 28 Resistor-capacitor MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description Internal LPO Nominal Type Frequency (kHz) 100 100 500 500 100 100 MOTOROLA ...
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... STATIC RAM (4T) — 224 BYTES USER EPROM — 6160 BYTES PERSONALITY EPROM — 64 BITS * High sink current capability * High source current capability † IRQ interrupt capability MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 16-BIT TIMER (1) INPUT CAPTURE (1) OUTPUT COMPARE 15-STAGE CORE TIMER SYSTEM WATCHDOG & ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description PB0/AN0 OSC1 17 OSC2 16 RESET 15 IRQ † PA0* 13 † PA1* 12 † PA2* 11 PB0/AN0 OSC1 25 OSC2 24 PC3* 23 PC2* 22 PC1* 21 PC0* 20 RESET 19 IRQ † PA0* 17 † PA1* 16 † PA2* 15 MOTOROLA ...
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... The selection of the crystal/ceramic resonator or RC oscillator configuration is done by product part number selection as described in Section 17. Ordering The frequency, f two to produce the internal operating frequency, f MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA is ground. The MCU operates from a single power SS A crystal as shown in Figure 1-3 A ceramic resonator as shown in ...
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... OSC2 R (a) Crystal or (b) RC Oscillator Connections Connections Figure 1-3. EPO Oscillator Connections Figure 1-3 (a) shows a typical oscillator circuit for an Figure 1-3 MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description MCU OSC1 OSC2 OSC2 UNCONNECTED EXTERNAL CLOCK (c) External Clock Source Connection (a) can be used for a ceramic MOTOROLA ...
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... When operating from this internal LPO, the other oscillator can be powered down by software to further conserve power. The selection of the LPO configuration is done by product part number selection as described in MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA (b). Section 17. Ordering Figure 1-3 (c). This oscillator can be selected via software. ...
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... V PP 15.14 PEPROM and EPROM Programming MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description . The RESET pin also SS pin requires an external PP pin is not used, PP pin contains an internal PP to program DD pin, except that active PP pin also applies to the I/O PP MOTOROLA ...
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... I/O port. This port is only available on the 28-pin MC68HC705JP7. All eight of these pins have high current source and sink capability. All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the MOR. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Interrupts. General Description General Description PA0–PA5 ...
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... General Description Advance Information 34 MC68HC705JJ7 • MC68HC705JP7 — REV 4 General Description MOTOROLA ...
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... Introduction This section describes the organization of the memory on the MC68HC705JJ7/MC68HC705JP7. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Memory Map Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 User and Interrupt Vector Mapping Random-Access Memory (RAM Erasable Programmable Read-Only Memory (EPROM COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory Section 2. Memory Advance Information ...
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... Figure 2-1. Memory Map and Figure 2-3 summarize: The first 32 addresses of the memory space, $0000–$001F, containing the I/O registers section One I/O register located outside the 32-byte I/O section, which is the computer operating properly register (COPR) mapped at $1FF0 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Memory MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Address Register Name $0000 Port A Data Register $0001 Port B Data Register $0002 Port C Data Register * $0003 Analog MUX Register $0004 Port A Data Direction Register $0005 Port B Data Direction Register $0006 Port C Data Direction Register * $0007 ...
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... MUX1 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 DDRC3 DDRC2 DDRC1 DDRC0 RT1 CTOFR RTIFR Reserved U = Unaffected MOTOROLA PA0 PB0 PC0 RT0 1 Bit 0 0 ...
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... See page 92. Timer Control Register $0012 (TCR) See page 170. 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices. Figure 2-3. Register Summary (Sheet MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Bit Read: SPIE SPE LSBF Write: Reset: 0 ...
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... Bit Bit Bit Bit Bit Bit Bit Bit Reserved U = Unaffected MOTOROLA ...
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... Reserved COP and Security Register $1FF0 (COPR) See pages 43, 137, 156, and 188. 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices. Figure 2-3. Register Summary (Sheet MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Bit Read Write Reset: ...
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... Core Timer Interrupt Vector (LSB) $1FFA External IRQ Vector (MSB) $1FFB External IRQ Vector (LSB) $1FFC SWI Vector (MSB) $1FFD SWI Vector (LSB) $1FFE Reset Vector (MSB) $1FFF Reset Vector (LSB) Figure 2-4. Vector Mapping MC68HC705JJ7 • MC68HC705JP7 — REV 4 Memory MOTOROLA ...
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... Address: $1FF0 $1FF0 Read: Write: EPMSEC Reset security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Erasable Programmable Read-Only Memory (EPROM) Addresses $0700–$1EFF contain 6144 bytes of user EPROM. ...
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... Memory Advance Information 44 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Memory MOTOROLA ...
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... Introduction This section describes the central processor unit (CPU) registers. Figure 3-1 the memory map. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 3. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Index Register Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Condition Code Register .48 Arithmetic/Logic Unit (ALU .50 shows the five CPU registers. CPU registers are not part of ...
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... The CPU uses the accumulator to hold operands and results Bit Unaffected by reset Figure 3-2. Accumulator (A) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Central Processor Unit (CPU ACCUMULATOR ( INDEX REGISTER ( STACK POINTER (SP) 0 PCL PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR MOTOROLA Bit 0 ...
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... A subroutine uses two stack locations; an interrupt uses five locations. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 3-3. In the indexed addressing modes, the CPU uses the byte in Bit Unaffected by reset Figure 3-3 ...
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... Figure 3-5. Program Counter (PC) Bit Unaffected Figure 3-6. Condition Code Register (CCR) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Central Processor Unit (CPU) Figure 3-5. The Bit Figure 3-6. The Bit MOTOROLA ...
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... Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. Reset has no effect on the carry/borrow flag. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Central Processor Unit (CPU) Central Processor Unit (CPU) Condition Code Register Advance Information ...
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... Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations. Advance Information 50 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Central Processor Unit (CPU) MOTOROLA ...
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... An interrupt temporarily stops normal program execution to process a particular event. An interrupt does not stop the execution of the instruction in progress, but takes effect when the current instruction completes its execution. Interrupt processing automatically saves the MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 External Interrupts ...
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... SPIE bit — I bit CPIE bit MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts Priority Vector (1 = Highest) Address 1 $1FFE–$1FFF Same priority $1FFC–$1FFD as instruction 2 $1FFA–$1FFB 3 $1FF8–$1FF9 4 $1FF6–$1FF7 5 $1FF4–$1FF5 6 $1FF2–$1FF3 MOTOROLA ...
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... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Stores the CPU registers on the stack in the order shown in Figure 4-1 Sets the I bit in the condition code register to prevent further interrupts Loads the program counter with the contents of the appropriate interrupt vector locations as shown in ...
Page 54
... INTERRUPT? NO ANALOG YES INTERRUPT? STACK PCL, PCH CCR NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CCR PCH, PCL INSTRUCTION? NO EXECUTE INSTRUCTION Figure 4-2. Interrupt Flowchart MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts SET I BIT MOTOROLA ...
Page 55
... NOTE: If the IRQ/V The IRQ/V and low level-triggered. External interrupt sensitivity is programmed with the LEVEL bit in the mask option register (MOR). MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA IRQ/V pin PP PA3–PA0 pins PP pin is not in use, it should be connected to the V PP ...
Page 56
... As long as any PP pin latches an external interrupt request. A subsequent PP pin returns to a logic 1 and then falls again to logic 0. PP MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts USER EPROM AND PEPROM TO BIH & BIL INSTRUCTION PROCESSING EXTERNAL INTERRUPT REQUEST MOTOROLA ...
Page 57
... NOTE: If the port A pins are enabled as external interrupts, then a high level on any PA0:3 pin will drive the state of the IRQ function such that the MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA pin can be affected if the external interrupt PP Interrupts Interrupts External Interrupts ...
Page 58
... OM2 OM1 Unimplemented R Figure 4-4. IRQ Status and Control Register (ISCR External interrupt processing enabled 0 = External interrupt processing disabled MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts pin is PP pin returns Bit 0 IRQF IRQR Reserved U = Unaffected MOTOROLA ...
Page 59
... Writing to the IRQF bit has no effect. Reset clears the IRQF bit. The following conditions set the IRQ flag: The following conditions clear the IRQ flag: MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table Table 4-2. Oscillator Selection Oscillator Low-Power OM2 ...
Page 60
... The RTIF flag bit can be reset by writing a logical 1 to the RTIFR bit in the CTSCR reset of the device. Advance Information Clear IRQF flag bit effect Timer overflow interrupt Real-time interrupt MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts MOTOROLA ...
Page 61
... A timer overflow interrupt occurs if the timer overflow flag (TOF) becomes set while the timer overflow interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the TCR. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Input capture Output compare Timer counter overflow ...
Page 62
... Voltage on positive input of comparator 1 is greater than the voltage on the negative input of comparator 1. Voltage on positive input of comparator 2 is greater than the voltage on the negative input of comparator 2. Trigger of the input capture interrupt from the programmable timer as described in 4.8.1 Input Capture Interrupt MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts MOTOROLA ...
Page 63
... For the analog subsystem to generate an interrupt using the input capture function of the programmable timer, the ICEN enable bit in the ACR, and the ICIE and IEDG bits in the TCR must all be set. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Interrupts Interrupts Analog Interrupts ...
Page 64
... Interrupts Advance Information 64 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Interrupts MOTOROLA ...
Page 65
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power-On Reset (POR Computer Operating Properly (COP) Reset Low-Voltage Reset (LVR Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . 72 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 External Oscillator and Internal Low-Power Oscillator ...
Page 66
... Fetch of an opcode from an address not in the memory map (illegal address reset) shows a block diagram of the reset sources and their INTERNAL DATA BUS INTERNAL ADDRESS BUS Figure 5-1. Reset Sources MC68HC705JJ7 • MC68HC705JP7 — REV 4 Resets S TO CPU RST D AND RESET SUBSYSTEMS LATCH R INTERNAL CLOCK MOTOROLA ...
Page 67
... RESET pin should activate external reset function is not required, the RESET pin should be left unconnected. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA DD generates an external reset. This pin is connected to a Schmitt Resets Power-On Reset pin generates a power-on reset ...
Page 68
... COPR register at location $1FF0. The COPC bit, shown in Figure Advance Information 68 Initial power-on reset (POR) function COP watchdog timer reset Low-voltage reset (LVR) Illegal address detector for the internal POR circuit to detect the next rise of POR 5- write-only bit. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Resets must DD MOTOROLA ...
Page 69
... RESET pin low for three to four cycles of the internal bus. The COP watchdog reset function can be enabled or disabled by programming the COPEN bit in the MOR security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. MC68HC705JJ7 • MC68HC705JP7 — REV 4 ...
Page 70
... Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF Clears the stop latch, enabling the CPU clock Clears the wait latch, bringing the CPU out of the wait mode MC68HC705JJ7 • MC68HC705JP7 — REV 4 Resets supply voltage DD MOTOROLA ...
Page 71
... A reset clears the COP watchdog timeout counter. 1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Clears bits in data direction registers configuring pins as inputs: – DDRA5–DDRA0 in DDRA for port A – DDRB7–DDRB0 in DDRB for port B – ...
Page 72
... Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is set Clears all the bits in the analog control register (ACR) Clears all the bits in the analog status register (ASR) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Resets MOTOROLA ...
Page 73
... OM2 = 1) which has these effects on the oscillators: • • • MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA The internal low-power oscillator is enabled and selected. The external oscillator is disabled. The CPU bus clock is driven from the internal low-power oscillator. Resets Resets Reset States ...
Page 74
... Resets Advance Information 74 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Resets MOTOROLA ...
Page 75
... Introduction This section describes the operation of the device with respect to the oscillator source and the low-power modes: • • • • MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 6. Operating Modes Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Data-Retention Mode ...
Page 76
... OM1 Unimplemented Figure 6-1. IRQ Status and Control Register (ISCR) for more details. 6-1. Reset clears OM1 and sets OM2, which selects the LPO MC68HC705JJ7 • MC68HC705JP7 — REV 4 Operating Modes Bit 0 IRQF IRQR Reserved Section 4. MOTOROLA ...
Page 77
... This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Refer to more details. 6.4 Low-Power Modes Four modes of operation reduce power consumption: • • • • Figure 6-2 MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table 6-1. Oscillator Selection Oscillator Low-Power OM2 OM1 Selected Oscillator 0 0 Internal ...
Page 78
... WAIT CLEAR I BIT IN CCR. SET IRQE BIT IN ISCR. TURN OFF CPU CLOCK. KEEP OTHER MODULE CLOCKS ACTIVE. YES EXTERNAL RESET? NO YES EXTERNAL INTERRUPT? NO CORE YES TIMER INTERRUPT? NO PROG. YES TIMER INTERRUPT? NO YES SIOP INTERRUPT? NO YES ANALOG INTERRUPT? NO YES COP RESET? NO MOTOROLA ...
Page 79
... The STOP instruction does not affect any other bits, registers, or I/O lines. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Turns off the central processor unit (CPU) clock and all internal clocks by stopping both the external pin oscillator and the internal low-power oscillator. The selection of the oscillator by the OM1 and OM2 bits in the ISCR is not affected ...
Page 80
... Stops the CPU clock which drives the address and data buses, but allows the selected oscillator to continue to clock the core timer, programmable timer, analog subsystem, and SIOP MC68HC705JJ7 • MC68HC705JP7 — REV 4 Operating Modes pin — A high-to-low PP 6.4.3 Halt Mode. MOTOROLA ...
Page 81
... When the MCU exits the wait mode, there is no delay before code executes like occurs when exiting the stop or halt modes. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA An external interrupt signal on the IRQ/V transition on the IRQ/V pin loads the program counter with the PP contents of locations $1FFA and $1FFB ...
Page 82
... To take the MCU out of the data retention mode: 1. Return V 2. Return the RESET pin to a logic 1. Advance Information 82 voltage. The RESET pin must remain low DD continuously during data retention mode. to normal operating voltage. DD MC68HC705JJ7 • MC68HC705JP7 — REV 4 Operating Modes voltages as low as 2.0 DD MOTOROLA ...
Page 83
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 7. Parallel Input/Output Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Port Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Data Direction Register Pulldown Register Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Data Direction Register Pulldown Register Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 PB0, PBI, PB2, and PB3 Logic ...
Page 84
... Individual programmable pulldown devices High current sinking capability on all port A pins, with a maximum total for port A High current sourcing capability on all port A pins, with a maximum total for port A External interrupt capability (pins PA3–PA0) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output MOTOROLA ...
Page 85
... PA5–PA0 — Port A Data Bits These read/write bits are software programmable. Data direction of each bit is under the control of the corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $0000 Bit ...
Page 86
... DDRA5 DDRA4 Unimplemented Figure 7-2. Data Direction Register A (DDRA Corresponding port A pin configured as output and pulldown device disabled 0 = Corresponding port A pin configured as input MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output DDRA3 DDRA2 DDRA1 DDRA0 MOTOROLA Bit 0 0 ...
Page 87
... Writing to this write-only bit controls the port C pulldown devices on the lower four bits (PC0–PC3). Reading these pulldown register A bits returns undefined data. Reset clears bit PDICL. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns $0010 ...
Page 88
... Corresponding port A pin pulldown device turned on if pin has been programmed by the DDRA input Interrupts. pin, not the state of the internal IRQ signal. PP MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output pin. The active interrupt state for PP pin as described in PP MOTOROLA ...
Page 89
... PA1 0 PA2 PA3 1 PA4 PA5 ( DDRA can always be read or written. 2. Don’t care MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table 7-1 summarizes the operations of the port A pins. DATA DIRECTION REGISTER A BIT DDRAx PORT A DATA REGISTER BIT PAx PULLDOWN REGISTER A BIT PDIAx MASK OPTION REG ...
Page 90
... SDO AN4 SCK SDI SDO TCMP SCK SDI SDO CMP1 Figure 7-5. Port B Data Register (PORTB) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output Bit 0 PB3 PB2 PB1 PB0 AN3 AN2 AN1 AN0 TCAP AN2 AN1 AN0 TCAP AN2 AN1 AN0 MOTOROLA ...
Page 91
... B pins as inputs. Address: Read: Write: Reset: DDRB7–DDRB0 — Port B Data Direction Bits These read/write bits control port B data direction. Reset clears the bits DDRB7–DDRB0. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $0005 Bit DDRB7 DDRB6 DDRB5 DDRB4 ...
Page 92
... Corresponding port B pin pulldown device turned off 0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB input MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output 7-7. Clearing the PDIB7–PDIB0 bits PDIB3 PDIB2 PDIB1 MOTOROLA Bit 0 DIB0 0 ...
Page 93
... If the DDRB configures the pin as an output, then the port data 2. If the DDRB configures the pin as an input, then reading the port 3. If DDRB configures the pin as an input and the pulldown device is MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Figure 7-8 DATA DIRECTION REGISTER B ...
Page 94
... BIT PB4 OLVL CMP1 PULLDOWN REGISTER B BIT PDIB4 MASK OPTION REG. ($1FF1) COP REGISTER ($1FF0) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output ANALOG SUBSYSTEM INPUT AN4 AND TIMER OUTPUT COMPARE PB4 AN4 TCMP HIGH SINK/ SOURCE CURRENT CAPABILITY PULLDOWN DEVICE MOTOROLA ...
Page 95
... If the comparator 1 output is the desired output function, then the 4. If the PB4 pin input to the analog subsystem or a digital MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA function, then the DDRB4 bit must be set, the PB4 data bit must be cleared, and the OPT bit in the COPR must be cleared. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit ...
Page 96
... PBx in Data Data Off PBx out Pin Data On PB4 in Pin Data Off PB4 in Pin Data Off PB4 in Data Data Off PB4 out Data Data Off PB4 out Data Data Off PB4 out 1 Data Off 1 Data Off Figure 7-10. The operations of 7-3. MOTOROLA Pin 1 1 ...
Page 97
... If the SIOP function is terminated by clearing the SPE bit in the 4. If the PB5/SDO pin digital input, then both the SPE bit the PB5/SDO pin digital output, then the SPE bit in the MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA V DD DATA DIRECTION ...
Page 98
... PB6 data register bits are still accessible to the CPU and can be altered or read without affecting the SIOP functionality. However, if the DDRB6 bit is cleared, reading the PB6 data register will return the current state of the PB6/SDI pin. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output Figure 7-11. The operations of 7-3. PB6 SDI PULLDOWN DEVICE MOTOROLA ...
Page 99
... READ $0001 WRITE $0011 RESET MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA SCR, then the last conditions stored in the DDRB6, PDIB6, and PB6 register bits will then control the PB6/SDI pin. the SCR and the DDRB6 bit must be cleared. Depending on the external application, the pulldown device may also be disabled by setting the PDIB6 pulldown inhibit bit ...
Page 100
... PDIB7 pulldown inhibit bit. SCR must be cleared and the DDRB7 bit must be set. The pulldown device will be disabled when the pin is set as an output. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output MOTOROLA ...
Page 101
... DDRB can always be read or written. 2. Don’t care 7.5 Port C (28-Pin Versions Only) Port 8-bit, general-purpose, bidirectional I/O port with these features: • • • MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Port B (1) PDIBx DDRBx ...
Page 102
... C pin. A reset initializes all DDRC bits to logic 0s, configuring all port C pins as inputs. Advance Information 102 $0002 Bit PC7 PC6 PC5 PC4 Unaffected by reset Figure 7-13. Port C Data Register (PORTC) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output Bit 0 PC3 PC2 PC1 PC0 MOTOROLA ...
Page 103
... When a port C pin is programmed as an input, reading the port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its DDR bit. operations of the port C pins. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $0006 Bit ...
Page 104
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output PCx HIGH SINK/SOURCE CURRENT CAPABILITY PULLDOWN DEVICE Result on Port C Pins Write Pulldown Pin Data On PCx in Data Off PCx in Data Off PCx in Data Off PCx out Data On PCx in Data Off PCx in Data Off PCx in Data Off PCx out MOTOROLA ...
Page 105
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Do not use read-modify-write instructions on pulldown register Avoid glitches on port pins by writing to the port data register before changing data direction register bits from a logic logic 1. Avoid a floating port input by clearing its pulldown register bit before changing its data direction register bit from a logic logic 0 ...
Page 106
... Parallel Input/Output Advance Information 106 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Parallel Input/Output MOTOROLA ...
Page 107
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 8. Analog Subsystem Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Analog Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . . 132 Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . 133 Internal Absolute Reference . . . . . . . . . . . . . . . . . . . . . 133 External Absolute Reference . . . . . . . . . . . . . . . . . . . . . 134 Ratiometric Voltage Readings ...
Page 108
... Direct digital output of comparator 1 to the PB4 pin Output compare from the 16-bit programmable timer Timer overflow from the 16-bit programmable timer Direct software control via a register bit MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem Figure 8- external voltage MOTOROLA ...
Page 109
... MUX3 PORTB LOGIC PB4 AN4 TCMP MUX4 V AOFF + – Figure 8-1. Analog Subsystem Block Diagram MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA PB3/AN3/TCAP CHG CHARGE CURRENT CONTROL LOGIC I DISCHG + COMP2 – INTERNAL INV DIODE SAMPLE CAP ...
Page 110
... Software polling of the comparator output using software loop time 8-2. $0003 Bit HOLD DHOLD INV VREF Figure 8-2. Analog Multiplex Register (AMUX) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem Bit 0 MUX4 MUX3 MUX2 MUX1 Figure 8-3. This allows the Table 8-1. SS MOTOROLA ...
Page 111
... Divide input 0 1 Direct input 1 0 Internal temperature 1 1 diode 1. Don’t care MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA V DD PB0 INTERNAL DIODE CHANNEL SELECTION BUS OFFSET Figure 8-3. Comparator 2 Input Circuit Table 8-1. Comparator 2 Input Sources OPT ...
Page 112
... CPF1 or CPF2 flags with respect to the external port pins. Advance Information 112 1 = The voltage comparators are internally inverted The voltage comparators are not internally inverted. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem and the internal sample SS following the reset. SS Figure 8-4. This bit MOTOROLA ...
Page 113
... NOTE: The V voltage generated by the total chip current passing through the package bond wires and lead frame that are attached to the single V offset raises the internal V MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA RISE WHEN V+ V+ > V– V– INV = 0 Figure 8-4 ...
Page 114
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem MUX to the SS reference line. SS offset gets placed on the SS line. Under SS PB2/AN2 PB1/AN1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z On Hi-Z On Hi-Z Hi Hi-Z Hi Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z On Hi-Z On Hi-Z Hi Hi-Z Hi MOTOROLA Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi ...
Page 115
... Reset: CHG The CHG enable bit allows direct control of the charge current source and the discharge device and also reflects the state of the discharge device. This bit is cleared by a reset of the device. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA = 4.5 to 5.5 DD $001D Bit 7 6 ...
Page 116
... CHG bit is cleared. The CHG bit remains set 1 until the next time ICF occurs. The CHG bit remains 0 cleared until the next time OCF occurs. The CHG bit remains set 1 until the next time ICF occurs. MOTOROLA ...
Page 117
... Powering down a comparator will drop the supply current. This bit is cleared by a reset of the device. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Connects the CPF2 flag bit to the timer input capture register 0 = Connects the PB3/AN3 pin to the timer input capture register ...
Page 118
... Writing a logic 0 powers down voltage comparator Writing a logic 1 powers up the ramping current source and enables the discharge device on the PB0/AN0 pin Writing a logic 0 powers down the ramping current source and disables the discharge device on the PB0/AN0 pin. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem MOTOROLA ...
Page 119
... INV bit in the AMUX register. This bit is reset by writing a logic 1 to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $001E Bit ...
Page 120
... V), the output of the comparator is indeterminate DD Hold Enables approximately 100 mV offset to be added to the sample voltage when both the HOLD and DHOLD control bits are cleared 0 = Connects the bottom of the sample capacitor to V MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem . The VOFF bit is SS 8.11 SS MOTOROLA ...
Page 121
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Enables the output of comparator ORed with the PB4 data bit and OLVL bit, if the DDRB4 bit is also set 0 = Disables the output of comparator 1 from affecting the PB4 pin 1 = The voltage on the positive input on comparator 2 is higher than the voltage on the negative input of comparator 2 ...
Page 122
... PB4/AN4 PB3/AN3 UNKNOWN OR REFERENCE PB2/AN2 SIGNALS PB1/AN1 PB0/AN0 RAMP CAP Figure 8-7. Single-Slope A/D Conversion Method MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem –1.5 Vdc DD UNKNOWN VOLTAGE ON (–) INPUT DISCHARGE TIME TO RESET CAPACITOR + MC68HC705JJ7 MC68HC705JP7 V SS MOTOROLA ...
Page 123
... Where MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Charging current to external capacitor Value of the external capacitor Clock rate for timing function Any prescaling of the clock to the timing function Desired resolution ...
Page 124
... OSC EXT FS CHG CHG EXT levels, the discharge time should SS MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem , can be combined CHG ) of the CHG , OSC OSC , conversion OSC OSC . This discharge SS MOTOROLA ...
Page 125
... Figure 8-11 • • • • MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA gives the range of values of each parameter in the A/D timing Table 8-5 gives some A/D conversion examples for using the signal names and parameters given in Manual start and stop (mode 0) Manual start and automatic discharge (mode 1) ...
Page 126
... Max Units V –1.5 — –1.5 — 15.10 Analog Subsystem and 15.11 Analog 15.10 Analog Subsystem and 15.11 Analog 2.56 0.128 10.24 0.512 ms 40.96 2.048 (1) 8.196 120 32.768 (1) 120 0.1 2.0 1024 65536 Counts User defined User defined 15.12 Control Timing (5.0 Vdc) 15.13 Control Timing (3.0 Vdc) MOTOROLA F P ...
Page 127
... Programmable timer 10 1024 3.5 (TOF Programmable timer 12 4096 3.5 (TOF 1. Not usable as the value of C EXT MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA A/D Method Clock Source Low-power oscillator Software loop (12 bus cycles) cycles) External pin oscillator OSC Low-power oscillator (prescaler = 8) Mode External pin oscillator ...
Page 128
... Wait out t time. CHG None Software write MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem t DIS (MIN) V MAX CHG CHG EXT 5 1 Dependent Variable(s) Software time MAX DIS EXT Software CHG EXT MAX CHG EXT Software MOTOROLA ...
Page 129
... CAP X output trips, setting CPF2 and 3 CMP2, which clears CHG control bit in the ACR. Reset CPF2 by writing CPFR2. Figure 8-9. A/D Conversion — Manual/Auto Discharge Control (Mode 1) MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA t CHG Software/Hardware Action Software write Wait out minimum t time ...
Page 130
... CHG Timer ICF clears the CHG control bit in the ACR. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem V MAX CHG CHG EXT 2 Dependent Variable(s) Software time MAX DIS EXT Free-running timer counter overflow, f OSC CHG EXT MOTOROLA ...
Page 131
... CPF2 and CMP2, which causes an ICF from the timer and 3 clears the CHG control bit in ACR. Must clear CPF2 to trap next CPF2 flag. Load next OCF. Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3) MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA t DIS (MIN) t CHG 2 3 ...
Page 132
... REF is the supply source to the device (V REF –1.5 volts), then the external capacitor will DD MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem / ( OSCMIN CHGMAX OSCMAX CHGMIN ) / (N – REF OFF and V SS REF ) REF ) SS ), then the ratiometric DD MOTOROLA ...
Page 133
... In this case, the reference reading can be taken by setting the V register. This connects the channel selection bus to the V within the V divided input. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table is provided, the reference measurement point DD bit and clearing the MUX1:4 bits in the AMUX REF ...
Page 134
... Compare unknown with recent measurement from reference OR avoid use of divided input Sum two readings on reference or unknown using INV and INV control bit and divide by 2 (average of both) Average multiple readings on both the reference and the unknown voltage MOTOROLA ...
Page 135
... In this case the reference reading can be taken by setting the V AMUX register which connects the channel selection bus to the V In order to stay within the V select the 1/2 divided input. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table 8-7. As with absolute measurements, Accuracy Improvements Possible In Hardware Compare unknown with recent ...
Page 136
... Not DDRB2 = 0 1 affected affected DDRB3 = 0 DDRB0 = 0 2 ISEN = 0 ISEN = 0 DDRB1 = 0 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem Table 8-8. Both comparators can pin. PP Prog. Timer Port B Pin Input Pulldowns Capture Disabled Source PDIB2 = 1 Not PDIB3 = 1 affected PDIB0 = 1 ICEN = 0 PDIB1 = 1 IEDG = 1 MOTOROLA ...
Page 137
... Also, since voltage comparator 2 is always connected to two of the port B I/O pins, these pins should be configured as inputs and have their software programmable pulldowns disabled. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Figure 8-12, and the COE1 bit is set in the ASR at location $001E. $1FF0 Bit 7 ...
Page 138
... Advance Information 138 SS , for each degree centigrade rise in the temperature of the D pin such that it may appear to leak down or SS MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem and will have its voltage current. DD 8.3 Analog Multiplex to be sampled and SS MOTOROLA ...
Page 139
... If the pulldowns are enabled, they will create an approximate 100 A load to any analog source connected to the pin. In some cases, the analog source may be able to supply this current without causing any MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA return pin. This offset also provides a means to measure SS level regardless of the comparator offset to determine ...
Page 140
... V digital power supply or load currents from passing through any conductors which are the return paths for an analog signal. Advance Information 140 pin. Also, try to keep all the SS MC68HC705JJ7 • MC68HC705JP7 — REV 4 Analog Subsystem return for both the SS MOTOROLA ...
Page 141
... SIOP transmitted or received data. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Serial Clock (SCK 143 Serial Data Input (SDI 144 Serial Data Output (SDO) ...
Page 142
... REGISTER ERROR R FORMAT CONTROL (LSB OR MSB FIRST) SIOP DATA REGISTER (SDR) $000C INTERNAL M68HC05 BUS Figure 9-1. SIOP Block Diagram MC68HC705JJ7 • MC68HC705JP7 — REV 4 Simple Synchronous Serial Interface PORTB LOGIC PB7 SCK PORTB LOGIC PB6 SDI PORTB LOGIC PB5 SDO MOTOROLA ...
Page 143
... SCK, and the SDI latches data in on the rising edge of SCK. (CPHA = 0) MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Figure 9-2. When the CPHA is set, SCK will remain idle at a Figure 9-3. In both cases, the SDO changes data on ...
Page 144
... MSB first format or the LSB first format. Advance Information 144 BIT 1 BIT 2 BIT 3 BIT 4 (IDLE = 0) 100 ns BIT 1 BIT 2 BIT 3 BIT 4 Figure 9-3. SIOP Timing Diagram (CPHA = 1) Figure 9-3. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Simple Synchronous Serial Interface BIT 5 BIT 6 BIT 7 BIT 8 100 ns BIT 5 BIT 6 BIT 7 BIT 8 MOTOROLA ...
Page 145
... SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the state of the SPIF flag bit and will not terminate a serial interrupt once the interrupt sequence has started. Reset clears the SPIE bit. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA shows the position of each bit in the register and indicates the $000A Bit 7 ...
Page 146
... Serial peripheral enabled (port B I/O disabled Serial peripheral disabled (port B I/O enabled LSB transferred first 0 = MSB transferred first 1 = SIOP set up as master, SCK is an output 0 = SIOP set up as slave, SCK is an input MC68HC705JJ7 • MC68HC705JP7 — REV 4 Simple Synchronous Serial Interface MOTOROLA ...
Page 147
... SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which places the SIOP clock selection at the slowest rate. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Reset the SPIF flag bit effect 1 = SCK is idle low ...
Page 148
... Figure 9-5. SIOP Status Register (SSR Serial transfer complete, serial interrupt if the SPIE bit in SCR is set 0 = Serial transfer in progress or serial interface idle MC68HC705JJ7 • MC68HC705JP7 — REV 4 Simple Synchronous Serial Interface shows the position of each bit Bit MOTOROLA ...
Page 149
... Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted and/or received. bit in the register. This register is not affected by reset. Address: Read: Write: Reset: MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Illegal access of the SDR occurred illegal access of the SDR detected $000C Bit Bit 7 ...
Page 150
... Simple Synchronous Serial Interface Advance Information 150 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Simple Synchronous Serial Interface MOTOROLA ...
Page 151
... This section describes the operation of the core timer and the computer operating properly (COP) watchdog as shown by the block diagram in Figure MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 10. Core Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Core Timer Status and Control Register 153 Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . 155 COP Watchdog ...
Page 152
... BITS 0–7 OF 15-STAGE RIPPLE COUNTER CORE TIMER STATUS/CONTROL REGISTER RTI RATE SELECT MC68HC705JJ7 • MC68HC705JP7 — REV 4 Core Timer RESET INTERNAL CLOCK 2 OSC1 INTERNAL CLOCK 1024 CORE TIMER INTERRUPT REQUEST $0008 RESET POWER-ON RESET COP WATCHDOG RESET MOTOROLA ...
Page 153
... This read-only flag becomes set when the selected real-time interrupt (RTI) output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $0008 Bit CTOF ...
Page 154
... Core timer overflow interrupts disabled 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled 1 = Clear CTOF flag bit effect on CTOF flag bit 1 = Clear RTIF flag bit effect on RTIF flag bit Table 10-1. Because the selected RTI output drives the MC68HC705JJ7 • MC68HC705JP7 — REV 4 Core Timer MOTOROLA ...
Page 155
... After the startup delay (16 or 4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Real-Time Interrupt Period RTI (RTI) ...
Page 156
... The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage offset capability to sample capacitor in analog subsystem security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. Advance Information ...
Page 157
... Less than 1.5 More than 1.5 1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions. 2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction. 3. Don’t care MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table 10-2 summarizes recommended conditions for enabling pin exceeds 1 ...
Page 158
... Core Timer Advance Information 158 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Core Timer MOTOROLA ...
Page 159
... Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . 173 11.11 Timer Operation during Halt Mode . . . . . . . . . . . . . . . . . . . . . 173 MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 11. Programmable Timer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Alternate Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Timer Status Register ...
Page 160
... The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013. Advance Information 160 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer Figure 11-1. MOTOROLA ...
Page 161
... SUBSYSTEM ICEN CONTROL BIT RESET TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS Figure 11-1. Programmable Timer Overall Block Diagram MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA EDGE SELECT ICRH ($0014) ICRL ($0015) & DETECT LOGIC TMRH ($0018) TMRL ($0019) 16-BIT COUNTER 16-BIT COMPARATOR ...
Page 162
... COUNTER OVERFLOW (TOF) TIMER CONTROL REG. $0012 Figure 11-2. Programmable Timer Block Diagram MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer READ TMRL ($0019) TMRL TMR LSB INTERNAL 4 CLOCK (OSC 2) TIMER INTERRUPT REQUEST TIMER STATUS REG. $0013 INTERNAL DATA BUS Figure 11-3 are MOTOROLA ...
Page 163
... The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $0018 Bit ...
Page 164
... LATCH ACRL ($001B) READ ACRH ($001A) TMR LSB $FFFC 16-BIT COUNTER Figure 11-4. Alternate Counter Block Diagram are read-only locations which contain the current high and MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer INTERNAL DATA BUS READ ACRL INTERNAL 4 CLOCK (OSC 2) MOTOROLA ...
Page 165
... Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA $001A Bit ...
Page 166
... Figure 11-7. Input Capture Registers (ICRH and ICRL) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer INTERNAL DATA BUS READ ICRL INTERNAL 4 CLOCK (OSC 2) TIMER INTERRUPT REQUEST $0013 INTERNAL DATA BUS 11-7. The input capture edge Bit Bit Bit Bit 0 MOTOROLA ...
Page 167
... OLVL bit in the TCR, and it occurs when the value of the 16-bit free-running timer counter matches the value in the output compare registers shown in bits and are unaffected by reset. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 11-8. Software writes the selected value into the output compare Figure Programmable Timer Programmable Timer Output Compare Registers 11-9 ...
Page 168
... Bit Unaffected by reset MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer R/W OCRL EDGE PB4 SELECT AN4 DETECT TCMP LOGIC INTERNAL 4 CLOCK (OSC 2) TIMER INTERRUPT REQUEST $0013 INTERNAL DATA BUS MOTOROLA Bit 0 Bit 8 Bit 0 Bit 0 ...
Page 169
... Enable interrupts by clearing the I bit in the condition code register. A software example of this procedure is shown in 9B ... ... ... ... 9A MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA written. also clears the OCF flag bit in the TSR. Table 11-1. Output Compare Initialization Example SEI DISABLE INTERRUPTS ... ..... ... ..... 16 STA ...
Page 170
... Unimplemented Figure 11-10. Timer Control Register (TCR Input capture interrupts enabled 0 = Input capture interrupts disabled 1 = Output compare interrupts enabled 0 = Output compare interrupts disabled MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer Figure 11-10, performs the Bit IEDG OLVL Unaffected MOTOROLA ...
Page 171
... MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled 1 = Positive edge (low-to-high transition) triggers input capture 0 = Negative edge (high-to-low transition) triggers input capture 1 = Signal to TCMP pin goes high on output compare. ...
Page 172
... Resets have no effect on TOF. Advance Information 172 $0013 Bit ICF OCF TOF Unimplemented Figure 11-11. Timer Status Register (TSR) MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer Bit Unaffected MOTOROLA ...
Page 173
... When the MCU enters halt mode, the functions and states of the 16-bit programmable timer are the same as for wait mode described in 11.9 Timer Operation during Wait MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA pin, at which time the counter resumes from its stopped PP Mode. ...
Page 174
... Programmable Timer Advance Information 174 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Programmable Timer MOTOROLA ...
Page 175
... PEPROM subsystem. NOTE: In packages with no quartz window, the PEPROM functions as one-time programmable ROM (OTPROM). MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . 177 PEPROM Status and Control Register 178 PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 PEPROM Reading ...
Page 176
... INTERNAL DATA BUS Figure 12-1. Personality EPROM Block Diagram Advance Information 176 $000F RESET V PP ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 8-TO-1 ROW DECODER AND MULTIPLEXER RESET $000E MC68HC705JJ7 • MC68HC705JP7 — REV 4 Personality EPROM (PEPROM) V SWITCH PP ROW ZERO DECODER MOTOROLA ...
Page 177
... These read/write bits select one of 64 bits in the PEPROM as shown in PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0, selecting the PEPROM bit in row zero, column zero. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA The PEPROM bit select register (PEBSR) The PEPROM status and control register (PESCR) $000E Bit 7 ...
Page 178
... PEPROM data is a logic 0. pin to the selected PEPROM bit cell. When Programming voltage applied to array bit 0 = Programming voltage not applied to array bit MC68HC705JJ7 • MC68HC705JP7 — REV 4 Personality EPROM (PEPROM Bit PEPRZF Reserved U = Unaffected MOTOROLA ...
Page 179
... World Wide Web at: http://www.motorola.com/mcu/ NOTE: While the PEPGM bit is set and the V IRQ/V (erased). To program the PEPROM bits properly, the V than 4.5 Vdc. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Row zero selected 0 = Row zero not selected Table 12-1. PEPROM Bit Selection PEBSR $00 $ ...
Page 180
... EPROM bit select register (PEBSR temporary storage location such that subsequent reads of the PEBSR quickly yield that PEPROM byte. Advance Information 180 PP personality EPROM data is retrieved and stored. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Personality EPROM (PEPROM) pin. This sequence shows how to . EPGM MOTOROLA PP ...
Page 181
... Erase the PEPROM by exposing Ws/cm with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is a logic 0. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Personality EPROM (PEPROM) Personality EPROM (PEPROM) PEPROM Erasing 2 ...
Page 182
... Personality EPROM (PEPROM) Advance Information 182 MC68HC705JJ7 • MC68HC705JP7 — REV 4 Personality EPROM (PEPROM) MOTOROLA ...
Page 183
... EPROM security bit (EPMSEC). NOTE: In packages with no quartz window, the EPROM functions as one-time programmable ROM (OTPROM). MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 13. EPROM/OTPROM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . 184 Mask Option Register .185 EPROM Security Bit ...
Page 184
... EPROM programming power switched EPROM programming power switched off 1 = MOR programming power switched MOR programming power switched off MC68HC705JJ7 • MC68HC705JP7 — REV 4 EPROM/OTPROM Figure 13 Bit 0 0 ELAT MPGM EPGM Reserved for test pin to the PP pin PP MOTOROLA ...
Page 185
... Oscillator shunt resistor ( open) 4. STOP instruction (enable or disable) 5. Low-voltage reset (enable or disable) MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = Address and data buses configured for EPROM programming of the array. The address and data buses are latched in the EPROM array when a subsequent write to the array is made. ...
Page 186
... Software pulldown inhibited 0 = Software pulldown enabled 1 = Startup delay is 4064 bus cycles Startup delay is 16 bus cycles Oscillator configured with 2 M¾ shunt resistor 0 = Oscillator configured without a shunt resistor MC68HC705JJ7 • MC68HC705JP7 — REV 4 EPROM/OTPROM Bit 0 LVREN PIRQ LEVEL COPEN MOTOROLA ...
Page 187
... LEVEL — External Interrupt Sensitivity Bit This EPROM bit makes the external interrupt inputs level-triggered as well as edge-triggered MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA 1 = STOP instruction converted to WAIT instruction 0 = STOP instruction not converted to WAIT instruction 1 = LVR function enabled 0 = LVR function disabled 1 = PA3– ...
Page 188
... Figure 13-3. EPROM Security in COP and Security Register (COPR) EPMSEC — EPROM Security This EPROM write-only bit enables the access to the EPROM array security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. Advance Information ...
Page 189
... EPROM Programming A programming board is available from Motorola to download to the on-chip EPROM/OTPROM using the factory-provided programming software. Factory-provided software for programming the PEPROM is available on the World Wide Web at: http://www.motorola.com/mcu/ The programming software copies to the 6144-byte space located at EPROM addresses $0700–$1EFF and to the 16-byte space at addresses $1FF0– ...
Page 190
... EPROM bit is a logic 0. NOTE: Unlike many commercial EPROMs, an erased EPROM byte in the MCU will read as $00. All unused locations should be programmed as 0s. Advance Information 190 . MPGM MC68HC705JJ7 • MC68HC705JP7 — REV 4 EPROM/OTPROM pin. PP pin ultraviolet light MOTOROLA ...
Page 191
... M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Section 14. Instruction Set Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Immediate ...
Page 192
... The opcode is the first byte, and the immediate data value is the second byte. Advance Information 192 Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative MC68HC705JJ7 • MC68HC705JP7 — REV 4 Instruction Set MOTOROLA ...
Page 193
... The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...
Page 194
... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. ...
Page 195
... These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Register/memory instructions Read-modify-write instructions Jump/branch instructions Bit manipulation instructions Control instructions Table 14-1 ...
Page 196
... Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence be- cause it does not write a replacement value. MC68HC705JJ7 • MC68HC705JP7 — REV 4 Instruction Set Mnemonic ASL ASR (1) BCLR (1) BSET CLR COM DEC INC LSL LSR NEG ROL ROR (2) TST MOTOROLA ...
Page 197
... The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Instruction Set Instruction Set Instruction Types Advance Information ...
Page 198
... Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine MC68HC705JJ7 • MC68HC705JP7 — REV 4 Instruction Set Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR MOTOROLA ...
Page 199
... I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. MC68HC705JJ7 • MC68HC705JP7 — REV 4 MOTOROLA Table 14-4. Bit Manipulation Instructions Instruction Bit Clear Branch if Bit Clear ...
Page 200
... Stop Oscillator and Enable IRQ/V PP Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts MC68HC705JJ7 • MC68HC705JP7 — REV 4 Instruction Set Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI Pin STOP SWI TAX TXA WAIT MOTOROLA ...