P89C660 Philips Semiconductors, P89C660 Datasheet

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P89C660

Manufacturer Part Number
P89C660
Description
80C51 8-bit Flash microcontroller family
Manufacturer
Philips Semiconductors
Datasheet

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Semiconductors
Product data
Replaces P89C660/P89C662/P89C664 of 2001 Jul 19
and P89C668 of 2001 Jul 27
hilips
P89C660/P89C662/P89C664/P89C668
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP FLASH with 512B/1KB/2KB/8KB RAM
INTEGRATED CIRCUITS
2002 Oct 28

Related parts for P89C660

P89C660 Summary of contents

Page 1

... P89C660/P89C662/P89C664/P89C668 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP FLASH with 512B/1KB/2KB/8KB RAM Product data Replaces P89C660/P89C662/P89C664 of 2001 Jul 19 and P89C668 of 2001 Jul 27 hilips Semiconductors INTEGRATED CIRCUITS 2002 Oct 28 ...

Page 2

... The device also has four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. The added features of the P89C660/662/664/668 makes it a powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. ...

Page 3

... KB P89C664HBA P89C664HFA P89C664HBBD P89C664HFBD P89C668HBA P89C668HFA P89C668HBBD 2002 Oct 28 P89C660/P89C662/P89C664/ Serial Inter- faces – – – 32 8(2)/4 – – – 32 8(2)/4 – – – 32 8(2)/4 – – – 32 8(2)/4 VOLTAGE ...

Page 4

... CODE FLASH 0. KBYTE DATA RAM PORT 3 CONFIGURABLE I/Os PORT 2 CONFIGURABLE I/Os PORT 1 CONFIGURABLE I/Os PORT 0 CONFIGURABLE I/Os CRYSTAL OR OSCILLATOR RESONATOR 2002 Oct 28 P89C660/P89C662/P89C664/ ACCELERATED 80C51 CPU 6-CLK MODE (DEFAULT) 12-CLK MODE (OPTIONAL) FULL-DUPLEX ENHANCED UART TIMER 0 TIMER 1 TIMER 2 PROGRAMMABLE COUNTER ARRAY (PCA) WATCHDOG TIMER 2 I ...

Page 5

... RAM ADDR RAM REGISTER B ACC REGISTER PSEN ALE TIMING AND EA/V PP CONTROL RST PD OSCILLATOR XTAL1 XTAL2 2002 Oct 28 P89C660/P89C662/P89C664/ P0.0–P0.7 P2.0–P2.7 PORT 0 PORT 2 DRIVERS DRIVERS PORT 0 PORT 2 LATCH LATCH STACK POINTER TMP2 TMP1 ALU SFRs TIMERS PSW P.C.A. PORT 1 PORT ...

Page 6

... P2.0/A8 10 RST 25 P2.1/A9 11 P3.0/RxD 26 P2.2/A10 12 NIC* 27 P2.3/A11 13 P3.1/TxD 28 P2.4/A12 14 P3.2/INT0 29 P2.5/A13 15 P3.3/INT1 30 P2.6/A14 * NO INTERNAL CONNECTION 2002 Oct 28 P89C660/P89C662/P89C664/ ADDRESS AND DATA BUS T2 T2EX ADDRESS BUS SU01090 Low Quad Flat Pack Pin Function Pin Function 1 P1.5/CEX2 31 P2.7/A15 2 P1.6/SCL 32 PSEN 3 P1.7/SDA 33 ALE 4 ...

Page 7

... As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: I Alternate functions for P89C660/662/664/668 Port 1 include: T2 (P1.0): Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out) T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1 ...

Page 8

... O NOTE: To avoid “latch-up” effect at power-on, the voltage on any pin (other than V 2002 Oct 28 P89C660/P89C662/P89C664/ NAME AND FUNCTION NAME AND FUNCTION External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations held high, the device executes from internal program memory ...

Page 9

... B0H 1 PCON# Power Control 87H * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. – Reserved bits. 1. Reset value depends on reset source. 2002 Oct 28 P89C660/P89C662/P89C664/ BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB – – – – ...

Page 10

... EPROM programming equipment to operate at 12 clock periods per machine cycle, referred to in this datasheet as “12 clock mode”. Once 12 clock mode has been configured, it cannot be changed back to 6 clock mode. 2002 Oct 28 P89C660/P89C662/P89C664/ BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB D7 D6 ...

Page 11

... Power-Down. POWER-ON FLAG The Power-On Flag (POF) is set by on-chip circuitry when the V level on the P89C660/662/664/668 rises from The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power- warm start after Power-Down. The V ...

Page 12

... C serial port is identical to the I C serial port on the 8XC554, 8XC654, and 8XC652 devices. 2 Note that the P89C660/662/664/668 I C pins are alternate functions to port pins P1.6 and P1.7. Because of this, P1.6 and P1.7 on these parts do not have a pull-up structure as found on the 80C51. Therefore P1.6 and P1.7 have open drain outputs on the P89C660/662/664/668 ...

Page 13

... Address Register, S1ADR This 8-bit special function register may be loaded with the 7-bit slave address (7 most significant bits) to which SIO1 will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (00H) recognition. 2002 Oct 28 P89C660/P89C662/P89C664 ...

Page 14

... ISP/IAP Flash with 512B/1KB/2KB/8KB RAM P1.7 INPUT FILTER P1.7/SDA OUTPUT STAGE INPUT FILTER P1.6/SCL OUTPUT STAGE P1.6 Figure 3. I 2002 Oct 28 P89C660/P89C662/P89C664/ S1ADR ADDRESS REGISTER COMPARATOR S1DAT SHIFT REGISTER ARBITRATION & SYNC LOGIC TIMING & CONTROL LOGIC SERIAL CLOCK GENERATOR TIMER 1 OVERFLOW ...

Page 15

... SCL line is released. 3. The SCL line is released, and the serial clock generator commences with the mark duration. 2002 Oct 28 P89C660/P89C662/P89C664/ The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or ...

Page 16

... S1DAT contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from and write to 2002 Oct 28 P89C660/P89C662/P89C664/ this 8-bit, directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 defined state and the serial interrupt flag is set ...

Page 17

... If STA is set while SIO1 is already in a Master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed slave. 2002 Oct 28 P89C660/P89C662/P89C664/ INTERNAL BUS 8 BSD7 S1DAT Figure 6 ...

Page 18

... When SIO1 is in the addressed Slave Transmitter mode, state C8H will be entered after the last serial is transmitted (see Figure 11). 2002 Oct 28 P89C660/P89C662/P89C664/ When SI is cleared, SIO1 leaves state C8H, enters the not addressed Slave Receiver mode, and the SDA line remains at a high level ...

Page 19

... NOTES: 1. These frequencies exceed the upper limit of 100 kHz of the MHz/15 MHz the maximum I OSC MHz/30 MHz the maximum I OSC 2002 Oct 28 P89C660/P89C662/P89C664/ BIT FREQUENCY (kHz OSC 2 6 MHz 8 MHz 12 MHz 15 MHz 47 62 ...

Page 20

... B0H if the Slave mode was enabled (AA = logic 1). The appropriate action to be taken for each of these status codes is detailed in Table 4. After a repeated start condition (state 10H). SIO1 2002 Oct 28 P89C660/P89C662/P89C664/ may switch to the Master Receiver mode by loading S1DAT with SLA+R). Master Receiver mode In the Master Receiver mode, a number of data bytes are received from a slave transmitter (see Figure 9) ...

Page 21

... ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS Ç Ç Ç Ç Ç THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I n Figure 8. Format and States in the Master Transmitter mode 2002 Oct 28 P89C660/P89C662/P89C664/ MT Ç Ç Ç Ç Ç Ç S SLA W ...

Page 22

... ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS DATA A THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I n Figure 9. Format and States in the Master Receiver Mode 2002 Oct 28 P89C660/P89C662/P89C664/ MR Ç Ç Ç Ç Ç Ç Ç DATA A DATA Ç ...

Page 23

... ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS Ç Ç Ç Ç Ç n THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I Figure 10. Format and States in the Slave Receiver mode 2002 Oct 28 P89C660/P89C662/P89C664/ Ç Ç Ç Ç Ç Ç Ç S SLA W A DATA Ç ...

Page 24

... ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS n THIS NUMBER (CONTAINED IN S1STA) CORRESPONDS TO A DEFINED STATE OF THE I Figure 11. Format and States of the Slave Transmitter mode 2002 Oct 28 P89C660/P89C662/P89C664/ Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 25

... S1DAT action or no S1DAT action or no S1DAT action No S1DAT action or 38H Arbitration lost in SLA+R/W or Data bytes S1DAT action 2002 Oct 28 P89C660/P89C662/P89C664/ TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE STA STO SLA+W will be transmitted; ACK bit will be received ...

Page 26

... Data byte has been Read data byte or received; NOT ACK has i d NOT ACK h read data byte or been returned read data byte 2002 Oct 28 P89C660/P89C662/P89C664/ TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE STA STO SLA+R will be transmitted; ...

Page 27

... General Call; DATA byte has been DATA read data byte or received; NOT ACK has been returned read data byte or read data byte 2002 Oct 28 P89C660/P89C662/P89C664/ TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE STA STO Data byte will be received and NOT ACK will be ...

Page 28

... Last data byte in S1DAT has been transmitted ( S1DAT action or ACK has been received no S1DAT action or no S1DAT action 2002 Oct 28 P89C660/P89C662/P89C664/ TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE STA STO Switched to not addressed SLV mode; no recognition ...

Page 29

... STO flag must be set and SI must be cleared. This causes SIO1 to enter the “not addressed” Slave mode (a defined state) and to clear the STO flag (no other bits in S1CON are affected). The 2002 Oct 28 P89C660/P89C662/P89C664/ TO S1CON NEXT ACTION TAKEN BY SIO1 HARDWARE STA ...

Page 30

... SDA line is eventually released, a normal START condition is transmitted, state 08H is entered, and the serial transfer continues forced bus access occurs or a repeated START condition is transmitted while SDA is obstructed (pulled LOW), the SIO1 2002 Oct 28 P89C660/P89C662/P89C664/ BOTH MASTERS CONTINUE DATA A S WITH SLA TRANSMISSION ...

Page 31

... SDA line released (3) Successful attempt to send a Start condition; state 08H is entered Figure 14. Recovering from a Bus Obstruction Caused by a Low Level on SDA byte-oriented system driver is described in application note AN435. Please visit http://www.semiconductors.philips.com/products/all_appnotes.html 2002 Oct 28 P89C660/P89C662/P89C664/ (2) (3) (1) START CONDITION 31 Product data P89C668 ...

Page 32

... TH0 is an 8-bit timer only controlled by Timer 1 control bits (Timer 1) Timer/Counter 1 stopped. Figure 15. Timer/Counter 0/1 Mode Control (TMOD) Register 2002 Oct 28 P89C660/P89C662/P89C664/ Mode 1 Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 18 ...

Page 33

... Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Figure 17. Timer/Counter 0/1 Control (TCON) Register 2002 Oct 28 P89C660/P89C662/P89C664/ C TLn (5 Bits) C Control ...

Page 34

... Figure 18. Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload OSC d* T0 Pin TR0 Timer 0 Gate bit INT0 Pin OSC 6-clock mode 12-clock mode. Figure 19. Timer/Counter 0 Mode 3: Two 8-Bit Counters 2002 Oct 28 P89C660/P89C662/P89C664/ C TLn (8 Bits) C Control THn (8 Bits) C TL0 (8 Bits) C Control TH0 ...

Page 35

... EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. Figure 20. Timer/Counter 2 (T2CON) Control Register 2002 Oct 28 P89C660/P89C662/P89C664/ or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 22). When reset is applied (DCEN = 0), Timer 2 defaults to counting up ...

Page 36

... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 22. Timer 2 Mode (T2MOD) Control Register 2002 Oct 28 P89C660/P89C662/P89C664/ TR2 1 16-bit Auto-reload 1 ...

Page 37

... Figure 23. Timer 2 in Auto-Reload Mode (DCEN = 0) n* OSC C/ C/ PIN TR2 * 6-clock mode 12-clock mode. Figure 24. Timer 2 Auto Reload Mode (DCEN = 1) 2002 Oct 28 P89C660/P89C662/P89C664/ TL2 TH2 (8 BITS) (8 BITS) CONTROL TR2 RELOAD RCAP2L RCAP2H CONTROL ...

Page 38

... Figure 25 shows Timer 2 in baud rate generation mode. The baud rate generation mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. 2002 Oct 28 P89C660/P89C662/P89C664/ TL2 TH2 (8-bits) (8-bits) Control ...

Page 39

... NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 2002 Oct 28 P89C660/P89C662/P89C664/ Where f = Oscillator Frequency OSC To obtain the reload value for RCAP2H and RCAP2L, the above ...

Page 40

... The addressed slave will clear 2002 Oct 28 P89C660/P89C662/P89C664/ its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes ...

Page 41

... SEND enables the output of the shift register to the alternate output function line of P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At 2002 Oct 28 P89C660/P89C662/P89C664 ...

Page 42

... If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, 2002 Oct 28 P89C660/P89C662/P89C664/ whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in RxD. More About Modes 2 and 3 ...

Page 43

... RxD (Data Out TxD (Shift Clock) S3P1 S6P1 TI Write to SCON (Clear RI) RI Receive Shift RxD (Data In S5P2 TxD (Shift Clock) 2002 Oct 28 P89C660/P89C662/P89C664/ 80C51 Internal Bus SBUF Zero Detector Start Shift TX Control TX Clock T1 Send R1 RX Clock Receive RX Control Shift Start 1 ...

Page 44

... Data S1P1 Shift Start Bit TxD Reset RX Clock Start RxD D0 D1 Bit Bit Detector Sample Times Shift RI 2002 Oct 28 P89C660/P89C662/P89C664/ 80C51 Internal Bus TB8 SBUF CL Zero Detector Start Shift Data TX Control TX Clock T1 Send 16 Load RX Clock RI SBUF RX Control Shift ...

Page 45

... S1P1 Shift Start Bit TxD Stop Bit Gen. 16 Reset RX Clock Start RxD D0 D1 Bit Bit Detector Sample Times Shift RI 2002 Oct 28 P89C660/P89C662/P89C664/ 80C51 Internal Bus TB8 SBUF CL Zero Detector Stop Bit Shift Data Gen. Start TX Control TX Clock T1 Send 16 Load R1 ...

Page 46

... S1P1 Shift Start Bit TxD Stop Bit Gen. 16 Reset RX Clock Start RxD D0 D1 Bit Bit Detector Sample Times Shift RI 2002 Oct 28 P89C660/P89C662/P89C664/ 80C51 Internal Bus TB8 SBUF CL Zero Detector Start Shift Data TX Control TX Clock T1 Send 16 Load R1 RX Clock SBUF ...

Page 47

... Slave 0 SADDR = 1100 0000 SADEN = 1111 1101 Given = 1100 00X0 2002 Oct 28 P89C660/P89C662/P89C664/ Slave 1 SADDR = 1100 0000 SADEN = 1111 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires bit 0 and it ignores bit 1 ...

Page 48

... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: *SMOD0 is located at PCON6. **f = oscillator frequency OSC 2002 Oct 28 P89C660/P89C662/P89C664/ SM2 REN TB8 RB8 ...

Page 49

... INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. Figure 34. UART Multiprocessor Communication, Automatic Address Recognition 2002 Oct 28 P89C660/P89C662/P89C664 ...

Page 50

... Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM Interrupt Priority Structure The P89C660/662/664/668 has an 8 source four-level interrupt structure (see Table 13). There are 4 SFRs associated with the four-level interrupt. They are the IE, IP, IEN1, and IPH (see Figures 35, 36, 37, and 38). The IPH (Interrupt Priority High) register makes the four-level interrupt structure possible ...

Page 51

... FUNCTION IEN1.7 — IEN1.6 — IEN1.5 — IEN1.4 — IEN1.3 — IEN1.2 — IEN1.1 — IEN1.0 ET2 Timer 2 interrupt enable bit. 2002 Oct 28 P89C660/P89C662/P89C664 PS1 PS0 PT1 PX1 2 C) interrupt priority bit. Figure 36. IP Registers PS1H PS0H ...

Page 52

... INC AUXR1 instruction without affecting the GF2 bit. 2002 Oct 28 P89C660/P89C662/P89C664/ The ENBOOT bit determines whether the BOOTROM is enabled or disabled. This bit will automatically be set if the status byte is non zero during reset or PSEN is pulled low, ALE floats high, and EA > ...

Page 53

... HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY) 2002 Oct 28 P89C660/P89C662/P89C664/ the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc ...

Page 54

... OSC/2 (6 CLOCK MODE) OR OSC/4 (12 CLOCK MODE) TIMER 0 OVERFLOW EXTERNAL INPUT (P1.2/ECI) IDLE PCA TIMER/COUNTER MODULE 0 MODULE 1 MODULE 2 MODULE 3 MODULE 4 CMOD.0 ECF 2002 Oct 28 P89C660/P89C662/P89C664/ CH 16–BIT UP COUNTER DECODE 11 CIDL WDTE –– –– –– –– CCF4 CCF3 Figure 41 ...

Page 55

... User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 2002 Oct 28 P89C660/P89C662/P89C664/ – – ...

Page 56

... ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 48). High Speed Output Mode In this mode, the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA 2002 Oct 28 P89C660/P89C662/P89C664/ CAPPn CAPNn MATn TOGn 5 ...

Page 57

... ECOMn 0 CF WRITE TO RESET CCAPnH CCAPnH WRITE TO CCAPnL 0 1 ENABLE 16–BIT COMPARATOR CH PCA TIMER/COUNTER –– 2002 Oct 28 P89C660/P89C662/P89C664/ –– CCF4 CCF3 CCF2 CCF1 (TO CCFn) CAPTURE CAPPn CAPNn MATn TOGn PWMn Figure 47. PCA Capture Mode CR –– ...

Page 58

... Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM WRITE TO RESET CCAPnH CCAPnH WRITE TO CCAPnL 0 1 ENABLE 16–BIT COMPARATOR CH PCA TIMER/COUNTER –– –– ECOMn 2002 Oct 28 P89C660/P89C662/P89C664 –– CCF4 CCF3 CCF2 CCAPnL (TO CCFn) MATCH CL ECOMn CAPPn CAPNn MATn TOGn 0 0 Figure 49 ...

Page 59

... PCA timer, 2. periodically change the PCA timer value so it will never match the compare values disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. 2002 Oct 28 P89C660/P89C662/P89C664/ CIDL WDTE –– –– –– CCAP4H ...

Page 60

... Main program goes here, but CALL WATCHDOG periodically. ; ;******************************************************************** ; WATCHDOG: CLR EA ; Hold off interrupts MOV CCAP4L, #00 ; Next compare value is within MOV CCAP4H 255 counts of the current PCA SETB EA ; timer value RET Figure 52. PCA Watchdog Timer Initialization Code 2002 Oct 28 P89C660/P89C662/P89C664/ 60 Product data P89C668 ...

Page 61

... Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM Expanded Data RAM Addressing The P89C660/662/664/668 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes expanded RAM (ERAM) (256 bytes for the ’ ...

Page 62

... Figure 54. Internal and External Data Memory Address Space with EXTRAM = 0 Hardware WatchDog Timer (One-Time Enabled with Reset-Out for P89C660/662/664/668) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The WDT is disabled at reset ...

Page 63

... In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations, produces reliable cycling. The P89C660/662/664/668 uses perform the Program/Erase algorithms. FEATURES – IN-SYSTEM PROGRAMMING (ISP) AND IN-APPLICATION PROGRAMMING (IAP) Flash EPROM internal program memory with Block Erase ...

Page 64

... Power-On Reset Code Execution The P89C660/662/664/668 contains two special Flash registers: the BOOT VECTOR and the STATUS BYTE. At the falling edge of reset, the P89C660/662/664/668 examines the contents of the Status Byte. If the Status Byte is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...

Page 65

... ASCII characters used to represent hexadecimal values and are summarized below: :NNAAAARRDD..DDCC<crlf> In the Intel Hex record, the “NN” represents the number of data bytes in the record. The P89C660/662/664/668 will accept (10H) data bytes. The “AAAA” string represents the address of the , V , and V ...

Page 66

... MHz cc = checksum Example: :0100000210ED 2002 Oct 28 P89C660/P89C662/P89C664/ P89C660/662/664/668 with information required to generate the proper timing. Record type 02 is provided for this purpose. COMMAND/DATA FUNCTION (dd = 10h = 16, used for 16.0–16.9 MHz) 66 Product data P89C668 ...

Page 67

... Example: :0500000440004FFF0069 2002 Oct 28 P89C660/P89C662/P89C664/ COMMAND/DATA FUNCTION 0k to 8k, 00H 8k to 16k, 20H erase block 4 erase boot vector and status byte (inhibit writing to Flash) (inhibit Flash verify) (disable external memory) program security bit 2 program boot vector with 0FCH display 4000– ...

Page 68

... Load of Baud Rate” function code hh = high byte of Timer low byte of Timer checksum Example: :02000006F500F3 2002 Oct 28 P89C660/P89C662/P89C664/ COMMAND/DATA FUNCTION read signature byte – device Product data P89C668 (C2H) ...

Page 69

... ERSBLK: 2002 Oct 28 P89C660/P89C662/P89C664/ Using the Watchdog Timer (WDT) The 89C66x devices support the use of the WDT in IAP. The user specifies that the WDT fed by setting the most significant bit of the function parameter passed in R1 prior to calling PGM_MTP. The WDT function is only supported for Block Erase when using the Quick Block Erase ...

Page 70

... DPTR indicates security bit to program ***** WRSB1: ;***** Program Security Bit2 ***** ;***** DPTR indicates security bit to program ***** WRSB2: ;***** Program Security Bit3 ***** ;***** DPTR indicates security bit to program ***** WRSB3: 2002 Oct 28 P89C660/P89C662/P89C664/ PARAMETER MOV AUXR1,#20H ;set the ENBOOT bit MOV R0, #11 ;FOSC MOV R1,#04H ...

Page 71

... DPTR = address of byte to read Return Parameter ACC = value of byte read Sample routine: ;*****reads the Device Data (DData) ***** ;***** DData returned in ACC ***** ;***** DPTR holds address of byte to read ***** RDData: 2002 Oct 28 P89C660/P89C662/P89C664/ PARAMETER MOV AUXR1,#20H ;set the ENBOOT bit MOV R0,#11 ;FOSC MOV R1,#06H ...

Page 72

... R1 = 80h (WDT feed, Rx2 & 66x only) DPH = 00h DPL = 02h (device Return Parameter ACC = value of byte read Sample routine: ;*****reads the Device ID 2 (DID2) ***** ;***** DID2 returned in ACC RDDID2: 2002 Oct 28 P89C660/P89C662/P89C664/ PARAMETER MOV AUXR1,#20H ;set the ENBOOT bit MOV R0,#11 ;FOSC MOV R1,#00H ...

Page 73

... R1 = 87h (WDT feed, Rx2 & 66x only) DPH = 00h DPL = 02h (boot vector) Return Parameter ACC = value of byte read Sample routine: ;*****reads the Boot Vector (BV) ***** ;***** BV returned in ACC RDBV: 2002 Oct 28 P89C660/P89C662/P89C664/ PARAMETER MOV AUXR1,#20H ;set the ENBOOT bit MOV R0,#11 ;FOSC MOV R1,#07H ...

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... The security feature protects against software piracy and prevents the contents of the Flash from being read. The Security Lock bits are located in Flash. The P89C660/662/664/668 has 3 programmable security lock bits that will provide different levels of protection for the on-chip code and data (see Table 16). ...

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... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V 2002 Oct 28 P89C660/P89C662/P89C664/ RATING 0 to +70 or –40 to +85 –65 to +150 0 to +13.0 – ...

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... Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except pF). 11. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I while an input voltage above 3.0 V will be recognized as a logic 1. 2002 Oct 28 P89C660/P89C662/P89C664 TEST CONDITIONS 4.5 V < ...

Page 77

... Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. 2002 Oct 28 P89C660/P89C662/P89C664 5 ...

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... Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < Spikes on the SDA and SCL lines with a duration of less than 3 t SCL = 400 pF 1/f = one oscillator clock period at pin XTAL1. CLCL OSC 2002 Oct 28 P89C660/P89C662/P89C664 5 INPUT 7 t ...

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... Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz. 2002 Oct 28 P89C660/P89C662/P89C664 5 ...

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... Spikes on the SDA and SCL lines with a duration of less than 3 t SCL = 400 pF 1/f = one oscillator clock period at pin XTAL1. For 63 ns < t CLCL OSC 2 I C-bus specification for bit-rates up to 100 kbit/s. 2002 Oct 28 P89C660/P89C662/P89C664 5 INPUT 14 t CLCL 16 t ...

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... ALE PSEN t LLWL RD t LLAX t AVLL A0–A7 PORT 0 FROM RI OR DPL t AVWL PORT 2 2002 Oct 28 P89C660/P89C662/P89C664/ P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: t AVLL t LLPL t LLPL t PLPH ...

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... ALE t XLXL CLOCK t QVXH OUTPUT DATA 0 WRITE TO SBUF t XHDV INPUT DATA VALID CLEAR 0.45V 2002 Oct 28 P89C660/P89C662/P89C664/ t WHLH t WLWH t t WHQX QVWX t QVWH DATA OUT P2.0–P2.7 OR A8–A15 FROM DPF Figure 59. External Data Memory Write Cycle XHQX ...

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... I (mA Valid only within frequency specifications of the device under test 2002 Oct 28 P89C660/P89C662/P89C664/ V +0.1V LOAD V LOAD V –0.1V LOAD NOTE: For timing purposes, a port is no longer floating when a 100mV change from max for a logic ‘0’. load voltage occurs, and begins to float when a 100mV change from the loaded ...

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... V LOAD V LOAD V LOAD NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V 2002 Oct 28 P89C660/P89C662/P89C664/ repeated START condition STOP condition SU;DAT1 HD;DAT 2 Figure 65. Timing SI01 (I C) Interface 0 ...

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... V SS Figure 68. I Test Condition, Active Mode. CC All other pins are disconnected V CC 0.5V Figure 70. Clock Signal Waveform for I Figure 71. I NOTE: * Ports 1.6 and 1.7 should be connected to V exceed the I specification. OL1 2002 Oct 28 P89C660/P89C662/P89C664 P1.6 * (NC) P1.7 * CLOCK SIGNAL SU01261 Figure 69. I – ...

Page 86

... Philips Semiconductors 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM PLCC44: plastic leaded chip carrier; 44 leads 2002 Oct 28 P89C660/P89C662/P89C664/ 86 Product data P89C668 SOT187-2 ...

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... Philips Semiconductors 80C51 8-bit Flash microcontroller family 16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM LQFP44: plastic low profile quad flat package; 44 leads; body 1.4 mm 2002 Oct 28 P89C660/P89C662/P89C664/ 87 Product data P89C668 SOT389-1 ...

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... REVISION HISTORY Rev Date Description _4 20021028 Product data (9397 750 10403); replaces P89C660/P89C662/P89C664 of 2001 Jul 19 (9397 750 08584) and P89C668 of 2001 Jul 27 (9397 750 08651) Engineering Change Notice 853–2392 29118 (date: 20021028) Modifications: Integrated 89C668 in 89C66x datasheet Added more description ...

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... Semiconductors 2002 Oct 28 P89C660/P89C662/P89C664/ Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date ...

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