M30622 Mitsubishi, M30622 Datasheet - Page 140

• Manufacturer Part Number: M30622
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

UART2 Special Mode Register
Figure 1.19.26. Functional block diagram for IIC mode
In the first place, the control bits related to the IIC bus(simplified IIC bus) interface are explained.
Bit 0 of the UART special mode register (0377
Setting “1” in the IIC mode select bit (bit 0) goes the circuit to achieve the IIC bus interface effective.
Table 1.19.9 shows the relation between the IIC mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
Figure 1.19.26 shows the functional block diagram for IIC mode. Setting “1” in the IIC mode selection bit
(IICM) causes ports P7
output terminal SCL, and port P7
so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P7
getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA
transmission output in this mode goes to the value set in port P7
detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop
condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection
interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P7
refers to the interrupt that occurs when the rising edge of the SDA terminal (P7
terminal (P7
start condition detection, and set to “0” by the stop condition detection.
P7
P7
P7
P7
0
1
2
/TxD
/RxD
/CLK
0
Tentative Specifications REV.A
through P7
2
2
/SDA
2
/SCL
S
pecifications in this manual are tentative and subject to change.
1
0
) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
) is detected with the SCL terminal (P7
Noize
Filter
Noize
Filter
Noize
2
Filter
conforming to the simplified IIC bus
Selector
Selector
Selector
Falling edge
detection
0
Timer
, P7
UART2
Stop condition detection
Start condition detection
IICM=1
IICM=0
1
UART2
IICM=1
, and P7
I/O
I/O
Timer
IICM=0
UART2
D
T
(Port P7
Timer
Q
I/O
L-synchronous
output enabling bit
Q
2
Arbitration
R
IICM=1
IICM=0
respectively. A delay circuit is added to the SDA transmission output,
1
External clock
output data latch)
Internal clock
IICM=1
2
IICM=0
Data bus
to work as data transmission-reception terminal SDA, clock input-
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7
Port reading
delay
16
UART2
CLK
S
R Q
140
) is used as the IIC mode selection bit.
Transmission
register
Reception register
Note 1: In M30623(80-pin package), P7
1
Bus busy
UART2
UART2
) staying “H”. The stop condition detection interrupt
Bus collision
detection
9th pulse
D
D
T
T
Q
Q
1
of the direction register.
ACK
0
. The interrupt factors of the bus collision
IICM=1
IICM=0
IICM=1
IICM=0
IICM=1
NACK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IICM=0
UART2 reception/ACK
interrupt request
DMA1 request
Bus collision/start, stop
condition detection
interrupt request
UART2 transmission/
NACK interrupt
request
2
/CLK
0
) is detected with the SCL
2
Mitsubishi microcomputers
is not connected to external pin.
M16C / 62T Group
1
(SCL) results in
To DMA0, DMA1
To DMA0