M30622 Mitsubishi, M30622 Datasheet - Page 46

no-image

M30622

Manufacturer Part Number
M30622
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Manufacturer
Mitsubishi
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30622-109GP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
M30622ECFP
Manufacturer:
INFINEON
Quantity:
607
Part Number:
M30622ECFP
Manufacturer:
ST
0
Part Number:
M30622EECFP
Manufacturer:
MIT
Quantity:
20 000
Part Number:
M30622F8PA04GP
Manufacturer:
MIT
Quantity:
105
Part Number:
M30622F8PA04GP
Manufacturer:
RENESAS
Quantity:
1 000
Part Number:
M30622F8PA04GP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Part Number:
M30622F8PFP
Manufacturer:
MIT
Quantity:
20 000
Part Number:
M30622F8PFP#D5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PFP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PFP#U5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PFPD5
Manufacturer:
RENESAS
Quantity:
893
Part Number:
M30622F8PFPU3C
Manufacturer:
RENESAS
Quantity:
5 002
Part Number:
M30622F8PFPU5U
Manufacturer:
STM
Quantity:
4 667
Part Number:
M30622F8PGP
Manufacturer:
MIT
Quantity:
20 000
Status Transition of BCLK
Status Transition of BCLK
Table 1.13.4. Operating modes dictated by settings of system clock control registers 0 and 1
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division
select bit 0 (bit 6 at address 0006
(1) Division by 2 mode
(2) Division by 4 mode
(3) Division by 8 mode
(4) Division by 16 mode
(5) No-division mode
(6) Low-speed mode
(7) Low power dissipation mode
Invalid
Invalid
Invalid
CM17
The main clock is divided by 2 to obtain the BCLK.
The main clock is divided by 4 to obtain the BCLK.
The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have
stabilized before transferring from this mode to another mode.
The main clock is divided by 16 to obtain the BCLK.
The main clock is used as the BCLK.
f
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
f
C
C
0
1
1
0
is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
is the BCLK and the main clock is stopped.
Tentative Specifications REV.A
S
pecifications in this manual are tentative and subject to change.
Invalid
Invalid
Invalid
CM16
1
0
1
0
CM07
0
0
0
0
0
1
1
16
) is set to “1”. The following shows the operational modes of BCLK.
Invalid
Invalid
CM06
0
0
1
0
0
CM05
46
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
CM04
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
Operating mode of BCLK
Mitsubishi microcomputers
M16C / 62T Group

Related parts for M30622