ispPAC10-01PI Lattice Semiconductor, ispPAC10-01PI Datasheet

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... Single +5V Supply Signal Conditioning — Active Filters, Gain Stages, Summing Blocks — Analog Front Ends, 12-Bit Data Acq. Systems — Sensor Signal Conditioning Description The ispPAC10 is a member of the Lattice family of In- System Programmable analog circuits, digitally configured 2 via nonvolatile E CMOS technology. ...

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... OH Power Supplies V Operating Supply Voltage S I Supply Current S P Power Dissipation D Temperature Range Operation Storage Specifications ispPAC10 of one PACblock (second input unused OUT CONDITION Applied Either – V IN+ IN– - 10kHz, Referred to Input ...

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... These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this speci- fication is not implied. ispPAC10 Ordering Information Ordering Number ispPAC10-01PI ispPAC10-01SI CONDITION Differential F = 10kHz IN Single-Ended ...

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... Behavior is not predictable during either of these steps since the analog outputs are not clamped during a programming cycle. Usually, however, the outputs will slew to either 0V (Ground behavior is partially determined by conditions existing immediately prior to device reprogramming and intermediate configura- tions that occur during the process. Specifications ispPAC10 CONDITION Executed in Run-Test/Idle Executed in Run-Test/Idle ...

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... Manufacturing test pin. Connect to GND for proper circuit operation. Differential input pin Differential input pin Differential output pin OUT Differential output pin OUT Pin Configuration and V should not OUT- , 2.5V). OUT 5 Specifications ispPAC10 Description with respect to VREF OUT ). - OUT = V OUT , where differential where V ...

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... Frequency (Hz) Small Signal BW vs. Gain -15 -21 -27 -33 -39 1k 10k 100k 1M 10M Frequency (Hz) Capacitive Load Handling Specifications ispPAC10 CMR vs. Frequency 100 100 1k 10k 100k 1M Frequency (Hz) THD vs. Frequency (Gain=1) -40 Rload = 300 - ...

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... Frequency Variation (%) Large-Signal Response 1.0V Gain = 1 Load = No Load Large-Signal Response with 600pF Load 1.0V Gain = 1 Load = 600pF Specifications ispPAC10 46.46kHz Filter F Accuracy C 50 2000 Units PDIP Pkg Frequency Variation (%) ...

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... PAC-Designer, a Windows-based design environment. PAC-Designer includes an AC simulator for design veri- fication prior to programming. The user can download the design to the ispPAC10 at any time via the device’s IEEE Standard 1149.1 (JTAG) compliant serial port directly from the parallel port using an ispDOWNLOAD™ ...

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... VREF Figure 3. Output VREF IAF Input Offset Auto-Calibration. A unique feature of the ispPAC10 is its ability to automatically calibrate itself to achieve very low offset error. This is done utilizing on- chip circuitry to perform an auto-calibration (auto-cal) 9 (Minus Input). The common IN- ...

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... With this feature, the degrada- tion of device offset performance that could occur over time and temperature is dramatically reduced. Specifi- cally, this means one PACblock of an ispPAC10 in a gain configuration of one is guaranteed to never have an input offset error greater than 1mV, after being auto-cali- brated ...

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... F Examining this transfer function shows the pole fre- quency is (1/2 )(2g 62pF, then 600kHz options for feedback capacitance, there are at least 120 poles between 10kHz and 100kHz. 11 Specifications ispPAC10 C Feedback Enable 1pF to 62pF IA1 ...

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... Figure 8. F Figure 8. PACblock A V IN1 V OUT1 (OUT1) The result is a circuit whose transfer function is: The gains k this circuit can either amplify or attenuate an input signal. The one in the denominator is due Specifications ispPAC10 FB 1 PACblock 1 IA1 OA1 IA2 -1 16.05pF PACblock 2 -1 IA3 ...

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... F When used in a single-supply system where the system common mode voltage is near V directly connected to the ispPAC10 input. If the input signal does not have such a DC bias, then one needs to be added to the signal in order to accommodate the input requirements for the ispPAC10 coupled bias can be added to a signal by using a voltage divider circuit as shown for one-half of the differential input in Figure 10a ...

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... VREF OUT Single-ended Operation Single-ended signals may be connected to the ispPAC10 input and one of the two differential ispPAC10 outputs can be used to drive single-ended circuitry. So, in addi- tion to fully differential I/O, either the input, output or both may be used single-ended. Single-ended Input . To connect the ispPAC10 differen- ...

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... Theory of Operation (Continued) Input Common-Mode Voltage Range For the ispPAC10, both maximum input signal range and corresponding common-mode voltage range are a func- tion of the input gain setting. The maximum input voltage times the gain of an individual PACblock cannot exceed the output range of that block or clipping will occur. The maximum guaranteed input range 4V, with an extended typical range of 0 ...

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... PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface of the ispPAC10. A library of configurations is included with basic solutions and examples of advanced circuit techniques. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation ...

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... IEEE 1149.1 serial interface are described in the interface section of this data sheet. User Electronic Signature A user electronic signature (UES) feature is included in 2 the E memory of the ispPAC10. It contains 8 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. Curve Tools Options ...

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... Figure 14. Configuring the ispPAC10 “In-System” from a PC Parallel Port PAC-Designer Software Specifications ispPAC10 ispPAC10 and can be used in real time to check circuit operation as part of the design process. Input and output connections as well as a “breadboard” circuit area are provided to speed debugging of the circuit. ...

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... Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. For ispPAC10, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being per- formed ...

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... Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC10. The bit code of this instruction is defined to be all ones by the IEEE 1149.1 standard. The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO ...

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... Bypass (connect TDI to TDO). The optional IDCODE (identification code) instruction is incorporated in the ispPAC10 and leaves it in its func- tional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device type and version code (see Figure 17) ...

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... The same programming constraints apply to UBE as for PRGUSR. The bit code for this instruction is shown in Table 2. Specifications ispPAC10 The ADDUSR, BYPASS, EXTEST, IDCODE and SAMPLE/PRELOAD instructions are all executed in the Update-IR state. Other instructions: PRGUSR, VERUSR and UBE are executed upon entry of the Run-Test/Idle state ...

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... BSC (Dimensions in millimeters, shown in parenthesis, are for reference only) .292 (7.42) Top View .299 (7.59) Pin 1 .050 (1.27) BSC .697 (17.70) .712 (18.08) .014 (.35) .019 (.48) Specifications ispPAC10 28-Pin Plastic DIP Dimensions in Inches MIN./MAX. .280 /.300 (7.11 / 7.61) .020 (.51) MIN .180 (4.57) MAX .125 / .135 (3.17 / 3.43) .045 /.055 (1.14 / 1.40) .015 /.021 ( ...