ISPGDX240VA-9B388I Lattice Semiconductor, ISPGDX240VA-9B388I Datasheet
ISPGDX240VA-9B388I
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ISPGDX240VA-9B388I Summary of contents
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... Simulator Netlist Generation for Easy Board-Level Simulation Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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... I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices. Specifications ispGDX240VA In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs ...
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... I/O Cell 119 240 Input GRP 120 I/O Cells Inputs Vertical Outputs Horizontal Specifications ispGDX240VA The various I/O pin sets are also shown in the block diagram below. The and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by ...
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... MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard and D MUX inputs, and Specifications ispGDX240VA allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The relationship between the [N+i] adjacent cells and ...
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... User-Programmable I/Os The ispGDX240VA features user-programmable Data C/ Data D/ I/Os supporting either 3.3V or 2.5V output voltage level MUXOUT MUXOUT options. The ispGDX240VA uses a VCCIO pin to provide B29 B28 the 2.5V reference voltage when used. B30 B29 PCI Compatible Drive Capability B31 B30 ...
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... Decoders Buffers / Registers Data Path System Bus #2 Clock(s) Specifications ispGDX240VA Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXVA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs ...
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... OE3 Port #4 OE4 Note: All OE and SEL lines driven by external arbiter logic (not shown). Specifications ispGDX240VA Designing with the ispGDXVA As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as ...
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... PARAMETER V Supply Voltage CC V I/O Reference Voltage CCIO o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Dedicated Clock Capacitance 2 Erase/Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispGDX240VA 1 +70 C Commercial - +85 C Industrial A PACKAGE TYPE TYPICAL TQFP TQFP MINIMUM 10,000 8 MIN. MAX. 3.00 3.60 3.00 3.60 2 ...
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... V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1. Typical values are 3.3V and T CC Specifications ispGDX240VA Figure 8. Test Load GND to V CCIO(MIN) 1.5ns 10 CCIO(MIN CCIO(MIN) See Figure 8 Device Output * C L includes Test Fixture and Probe Capacitance. ...
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... An input driving four I/O cells at 40MHz results in a dynamic I 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. Specifications ispGDX240VA Over Recommended Operating Conditions CONDITION – ...
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... Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. Specifications ispGDX240VA Over Recommended Operating Conditions DESCRIPTION 1 ...
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... External Timing Parameters (Continued) ispGDX240VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the GRP Delay with increased GRP loads. These deltas ispGDX240VA Maximum Specifications ispGDX240VA apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder ...
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... Global Reset t 65 Global Reset to I/O Register Latch gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. Specifications ispGDX240VA 1 Over Recommended Operating Conditions 1 DESCRIPTION MIN. MAX. MIN. MAX. UNITS — ...
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... Clock Width ispGDXVA Timing Model OE MUX Expander Input MUX0 MUX1 GRP tgrp #33 CLKEN tioclkeg #64 CLK tioclk #60 Y0,1,2,3 tgclk #61 Y0,1,2,3, Enable Specifications ispGDX240VA DATA (I/O INPUT) CLK REGISTERED I/O OUTPUT CLKEN t en RESET wl REGISTERED I/O OUTPUT tgoe #58 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 MUX Expander Output tmuxcg #50 ...
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... The Design Manager consists of the Menu Bar, Tool Bar, Lattice’s ispGDX Development System Interface Specifications ispGDX240VA Status Bar and the work area. The figure below shows these elements of the ispGDX GUI. The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or “ ...
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... BUS_D.s1 = sel1; BUS_D.s0 = sel0; BUS_D.oe = oe; BUS_D.clk = clk; END Specifications ispGDX240VA This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over. Powerful Syntax Lattice’s ispGDX Design System uses simple, but power- ful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition ...
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... VHDL VITAL Output Download: .jed JEDEC Device Programming File Specifications ispGDX240VA Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. ...
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... TCK EPEN ispGDX 240VA Device Specifications ispGDX240VA when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. This allows ISP programming and BSCAN testing to take place as specified by the Instruction Table. When the pin is driven low, the JTAG TAP controller is driven to a reset state asynchronously ...
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... Clock DR Table 3. I/O Shift Register Order DEVICE TDI, TOE, Y2, Y3, RESET, Y1, Y0, I/O B20 .. B39, I C39, I D19, I/O B19 .. B0, ispGDX240VA I/O A39.. A0, I/O D39 .. D20, TDO Table 4. ispGDX240VA Device ID Codes DEVICE 32-BIT BOUNDARY SCAN ID CODE ispGDX240VA 0001, 0000, 0011, 0101, 0100, 0000, 0100, 0011 Specifications ispGDX240VA allows customers using boundary scan test to have full test capability with only a single BSDL file ...
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... Input Pin SCANIN (from previous Shift DR Clock DR Figure 12. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 Specifications ispGDX240VA Downlowad (ispDCD™), ispCODE ‘C’ routines or any third-party programmers. Contact Lattice Technical Sup- port to obtain more detailed programming information cell 1 1 Select-DR-Scan 0 ...
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... BSCAN test Capture register hold time t btuco BSCAN test Update reg, falling edge of clock to valid output t btuoz BSCAN test Update reg, falling edge of clock to output disable t btuov BSCAN test Update reg, falling edge of clock to output enable Specifications ispGDX240VA T T btsu bth T btcl ...
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... Signal Locations: ispGDX240VA Signal TOE L22 RESET L21 Y0/CLKEN0 M4 Y1/CLKEN1 L3 Y2/CLKEN2 M20 Y3/CLKEN3 M21 EPEN A11 TDI M1 TCK L1 TMS L2 TDO AB12 GND A1, A22, B2, B21, C3, C20, D4, D19, H9, H10, H11, H12, H13, H14, J8, J9, J10, J11, J12, J13, J14, J15, K8, K9, K10, K11, K12, K13, K14, K15, L8, L9, L10, L11, L12, L13, L14, L15, M8, M9, M10, M11, M12, M13, ...
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... I/O Locations: ispGDX240VA (Ordered by 388-Ball BGA Location) (This page intentionally left blank) Specifications ispGDX240VA 23 ...
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... Signal Configuration: ispGDX240VA ispGDX240VA 388-Ball fpBGA Signal Diagram I/O I/O I/O I/O I/O 1 GND A10 A13 I/O I/O I/O I/O I/O GND A12 I/O I/O I/O I/O I/O 3 GND D57 D59 A3 A7 A11 I/O I/O I/O I/O 4 GND VCC D55 D54 D56 A8 I/O I/O I/O I/O 5 D50 D53 D52 D58 I/O I/O I/O VCC 6 D47 D48 D49 I/O I/O I/O I/O VCC 7 D43 D44 ...
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... Note: The ispGDX240VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster, e.g. ispGDX240VA-4B388-7I. Specifications ispGDX240VA ispGDX 240VA X XXXX X COMMERCIAL ORDERING NUMBER ispGDX240VA-4B388 ispGDX240VA-7B388 INDUSTRIAL ORDERING NUMBER ispGDX240VA-7B388I ispGDX240VA-9B388I 25 Grade Blank = Commercial I = Industrial Package B388 = 388-Ball fpBGA 0212/gdx240va PACKAGE 388-Ball fpBGA 388-Ball fpBGA Table 2-0041A/gdx240va ...