M36L0R8060 ST Microelectronics, M36L0R8060 Datasheet

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M36L0R8060

Manufacturer Part Number
M36L0R8060
Description
256 Mbit (Multiple Bank / Multi-Level / Burst) Flash Memory 64 Mbit (Burst) PSRAM
Manufacturer
ST Microelectronics
Datasheet

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FEATURES SUMMARY
FLASH MEMORY
December 2004
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
ELECTRONIC SIGNATURE
PACKAGE
SYNCHRONOUS / ASYNCHRONOUS READ
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
MEMORY ORGANIZATION
DUAL OPERATIONS
SECURITY
1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
1 die of 64 Mbit (4Mb x16) Pseudo SRAM
V
V
Manufacturer Code: 20h
Top Device Code
M36L0R8060T0: 880Dh
Bottom Device Code
M36L0R8060B0: 880Eh
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
Synchronous Burst Read mode: 54MHz
Asynchronous Page Read mode
Random Access: 85ns
10µs typical Word program time using
Buffer Enhanced Factory Program
command
Multiple Bank Memory Array: 16 Mbit
Banks
Parameter Blocks (Top or Bottom
location)
program/erase in one Bank while read in
others
No delay between read and write
operations
64 bit unique device number
2112 bit user programmable OTP Cells
DDF
PP
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
= 9V for fast program
= V
CCP
= V
DDQ
= 1.7 to 1.95V
Figure 1. Package
PSRAM
BLOCK LOCKING
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
LOW POWER FEATURES
SYNCHRONOUS BURST READ/WRITE
All blocks locked at power-up
Any combination of blocks can be locked
with zero latency
WP
Absolute Write Protection with V
Page Size: 16 words
Subsequent read within page: 20ns
Temperature Compensated Refresh
(TCR)
Partial Array Refresh (PAR)
Deep Power-Down (DPD) Mode
F
for Block Lock-Down
M36L0R8060B0
M36L0R8060T0
TFBGA88 (ZAQ)
8 x 10mm
FBGA
PRELIMINARY DATA
PPF
= V
1/18
SS

Related parts for M36L0R8060

M36L0R8060 Summary of contents

Page 1

... DDF CCP DDQ – for fast program PP ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code M36L0R8060T0: 880Dh – Bottom Device Code M36L0R8060B0: 880Eh PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY SYNCHRONOUS / ASYNCHRONOUS READ – ...

Page 2

... M36L0R8060T0, M36L0R8060B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A23 Data Input/Output (DQ0-DQ15 Latch Enable (L Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Wait (WAIT Flash Chip Enable (E ) ...

Page 3

... Table 8. PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. TFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15 Table 9. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M36L0R8060T0, M36L0R8060B0 3/18 ...

Page 4

... M36L0R8060T0, M36L0R8060B0 SUMMARY DESCRIPTION The M36L0R8060T0 and M36L0R8060B0 com- bine two memory devices in a Multi-Chip Package: a 256-Mbit, Multiple Bank Flash memory, the M30L0R8000T0 or M30L0R8000B0, and a 64- Mbit PseudoSRAM, the M69KR096A. Recom- mended operating conditions do not allow more than one memory to be active at the same time. ...

Page 5

... A3 D A17 DQ8 DQ0 M36L0R8060T0, M36L0R8060B0 A19 DDF A23 PPF A20 DQ2 DQ10 DQ5 ...

Page 6

... M36L0R8060T0, M36L0R8060B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A23). Addresses are common inputs for the Flash memory and PSRAM components. The other lines (A23-A22) are inputs for the Flash memory component only. ...

Page 7

... See Load provides the power sufficient to carry the required V and erase currents. M36L0R8060T0, M36L0R8060B0 . CCP Program Supply Voltage kept in a low voltage range ( seen as a control input. In this case a volt- gives an absolute protection ...

Page 8

... M36L0R8060T0, M36L0R8060B0 FUNCTIONAL DESCRIPTION The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip En- able inputs: E for the Flash memory and E F the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4 ...

Page 9

... Any PSRAM mode is allowed Hi Hi M36L0R8060T0, M36L0R8060B0 , Flash Data Out PSRAM must be disabled. Flash Data Out PSRAM data in IL ...

Page 10

... The M36L0R8060T0 and M36L0R8060B0 contain a 256 Mbit Flash memory. For detailed information on how to use the device, refer to the PSRAM DEVICE The M36L0R8060T0 and M36L0R8060B0 contain a 64Mbit PSRAM. For detailed information on how to use the device, see the M69KR096A datasheet 10/18 M30L0R8000(T/B)0 datasheet which is available from your local STMicroelectronics distributor ...

Page 11

... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter PPFH M36L0R8060T0, M36L0R8060B0 Value Min Max –25 85 –25 85 – ...

Page 12

... M36L0R8060T0, M36L0R8060B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Table 4. Operating and AC Measurement Conditions Parameter ...

Page 13

... Note: 1. Sampled only, not 100% tested Dual Operation current is the sum of read and program or erase currents. DDF 3. The total standby current should be calculates as the sum of the Flash memory standby current plus the PSRAM standby current. M36L0R8060T0, M36L0R8060B0 Test Condition ...

Page 14

... M36L0R8060T0, M36L0R8060B0 Table 7. Flash Memory DC Characteristics - Voltages Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage Program Voltage-Logic PP1 PPF V V Program Voltage Factory PPH PPF V Program or Erase Lockout PPLK V V Lock Voltage ...

Page 15

... SE 0.400 FE1 millimeters Min Max 1.200 0.200 0.300 0.400 7.900 8.100 0.100 9.900 10.100 – – M36L0R8060T0, M36L0R8060B0 e b ddd A2 A1 BGA-Z42 inches Typ Min 0.0079 0.0335 0.0138 0.0118 0.3150 0.3110 0.2205 0.3937 0.3898 0.2835 0.3465 0.0315 – 0.0472 ...

Page 16

... M36L0R8060T0, M36L0R8060B0 PART NUMBERING Table 10. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage 1.7 to 1.95V DDF CCP DDQ Flash 1 Density 8 = 256 Mbits Flash 2 Density ...

Page 17

... Version 29-Jan-2004 0.1 First Issue TFBGA88 package fully compliant with the ST ECOPACK specification. Document status promoted from Target Specification to Preliminary Data. 09-Dec-2004 1.0 Flash memory and PSRAM data updated to the version 0.3 of the M30L0R8000x0 and to the version 3.0 of the M69KR096A datasheet. M36L0R8060T0, M36L0R8060B0 Revision Details 17/18 ...

Page 18

... M36L0R8060T0, M36L0R8060B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...

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