K4S161622H-TC55 Samsung semiconductor, K4S161622H-TC55 Datasheet
K4S161622H-TC55
Related parts for K4S161622H-TC55
K4S161622H-TC55 Summary of contents
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... SDRAM 16Mb H-die(x16) 16Mb H-die SDRAM Specification Samsung Electronics reserves the right to change products or specification without notice. Revision 1.5 August 2004 CMOS SDRAM Rev. 1.5 August 2004 ...
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... SDRAM 16Mb H-die(x16) Revision History Revision 0.0 (May, 2003) - Target spec release. Revision 0.1 (October, 2003) - Modified tRDL from 1CLK to 2CLK. Revision 0.2 (October, 2003) - Deleted AC parameter notes 5. Revision 0.3 (October, 2003) - Modified tRDL & deleted speed 200MHz. Revision 1.0 (November, 2003) - Revision 1.0 spec. release. Revision 1.1 (December, 2003) - Corrected PKG dimension ...
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... SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/ O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten- cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. K4S161622H-TC55 K4S161622H-TC60 K4S161622H-TC70 K4S161622H-TC80 Organization MAX Freq ...
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... SDRAM 16Mb H-die(x16) Package Physical Dimension #50 #1 0.10MAX [ ] 0.075MAX (0.875) #26 #25 20.95 ± 0.10 0.80TYP +0.10 +0.10 [0.80±0.08] 0.30 0.35 -0.05 -0.05 50Pin TSOP(II) Package Dimension CMOS SDRAM 0~8° 0.25 TYP +0.075 0.125 -0.035 1.20MAX 1.00 ± 0.10 0.05MIN Rev. 1.5 August 2004 ...
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... SDRAM 16Mb H-die(x16) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register 512K x 16 512K x 16 Column Decoder Latency & Burst Length Programming Register LWE ...
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... SDRAM 16Mb H-die(x16) PIN CONFIGURATION (TOP VIEW) PIN FUNCTION DESCRIPTION Pin Name CLK System Clock CS Chip Select CKE Clock Enable /AP Address Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask DQ ~ Data Input/Output ...
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... SDRAM 16Mb H-die(x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. ...
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... Self Refresh Current I CC6 Note : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622H- 70° Test Condition Burst Length =1 ≥t t ...
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... SDRAM 16Mb H-die(x16) AC OPERATING TEST CONDITIONS Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Output 870Ω (Fig Output Load Circuit AC CHARACTERISTICS (AC operating conditions unless otherwise noted) ...
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... SDRAM 16Mb H-die(x16) (AC operating conditions unless otherwise noted) Parameter CAS Latency=3 CLK cycle time CAS Latency=2 CAS Latency=3 CLK to valid output delay CAS Latency=2 Output data CAS Latency=3 CLK high pulse width CAS Latency=2 CAS Latency=3 CLK low pulse width CAS Latency=2 ...
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... MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. ...