HYS64T128020GU Infineon, HYS64T128020GU Datasheet - Page 24

• Manufacturer Part Number: HYS64T128020GU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: Infineon

4
Table 16
Parameter
Operating Current 0
One bank Active - Precharge;
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open;
inputs are FLOATING. MRS A12 bit is set to “0” (Fast Power-down Exit);
Active Power-Down Current
All banks open;
inputs are FLOATING. MRS A12 bit is set to “1” (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
RCD
RAS
RAS
RAS
CK
CK
=
=
=
=
=
=
t
t
CKmin.
CKmin
t
t
t
t
RASmax.
RASmax.
RASmax.
RCDmin.
., Refresh command every
, Refresh command every
I
I
,AL = 0, CL = CL
,
,
,
DD
DD
t
t
t
RP
RP
RP
t
tCK
Measurement Conditions
CK
Specifications and Conditions
=
=
=
=
=
t
t
t
RPmin.
RPmin.
RPmin.
t
t
CKmin.
CKmin.
; CKE is HIGH, CS is high between valid commands. Address inputs are
; CKE is HIGH, CS is high between valid commands. Address inputs are
; CKE is HIGH, CS is high between valid commands. Address inputs are
, CKE is LOW; Other control and address inputs are STABLE, Data bus
, CKE is LOW; Other control and address inputs are STABLE, Data bus
t
CK
min
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
.; CKE is HIGH, CS is high between valid commands. Address and
=
t
CKmin.
t
I
t
RFC
OUT
RFC
,
t
t
t
=
=
RC
= 0 mA, BL = 4,
CK
CK
1)2)
t
t
REFI
RFCmin.
=
=
=
t
t
t
RCmin
CKmin.
CKmin.
I
I
interval, CKE is LOW and CS is HIGH between valid
OUT
OUT
interval, CKE is HIGH, CS is HIGH between valid
.,
; Other control and address inputs are
; Other control and address inputs are STABLE,
= 0 mA.
= 0 mA.
t
RAS
24
=
t
CK
t
RASmin.
=
t
CKmin.
, CKE is HIGH, CS is high between
,
t
RC
=
I
t
DD
RCmin
min.
min.
min.
.
Specifications and Conditions
;
;
;
t
t
t
.,
CK
CK
CK
512 Mbit DDR2 SDRAM
t
RAS
=
=
=
t
t
t
CKmin
CKmin.
CKmin.
=
09122003-GZEK-H4J6
t
RASmin.
.;
;
;
Rev. 0.87, 2004-06
.
,
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D