RG82845M Intel, RG82845M Datasheet
RG82845M
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RG82845M Summary of contents
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... R ® Intel 845 Family Chipset-Mobile: 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) Datasheet April 2002 Order Number: 250687-002 ...
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... Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... R Contents 1. Overview .................................................................................................................................... 14 1.1. System Architecture ...................................................................................................... 15 1.2. Mobile Intel Pentium 1.2.1. 1.3. System Memory Interface ............................................................................................. 16 1.4. AGP Interface................................................................................................................ 18 1.5. Hub Interface................................................................................................................. 18 1.6. MCH-M Clocking ........................................................................................................... 18 1.7. System Interrupts .......................................................................................................... 19 2. Signal Description ...................................................................................................................... 20 2.1. Host Interface Signals ................................................................................................... 21 2.2. DDR Interface................................................................................................................ 23 2.3. Hub Interface Signals .................................................................................................... 24 2.4. AGP Interface Signals ................................................................................................... 24 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.5. Clocks, Reset, and Miscellaneous ................................................................................ 30 2.6. Voltage References, PLL Power ................................................................................... 31 2.7. Pin State Table .............................................................................................................. 31 3 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.5. 3.7.6. 3.7.7. 3.7.8. 3.7.9. 3.7.10. 3.7.11. 3.7.12. 3.7.13. 3.7.14. 3.7.15. 3.7.16. 3.7.17. 3.7.18. 3.7.19. 3.7.20. 3.7.21. 3.7.22. 3.7.23. 3.7.24. 3.7.25. 3.7.26. 3.7.27. 3.7.28. 3.7.29. 3.7.30. 3.7.31. 3.7.32. 3.7.33. 3.7.34. 3.7.35. 3.7.36. 3.7.37. 3.7.38. 3.7.39. 3.7.40. 3.8. AGP Bridge Registers – Device #1 ............................................................................... 85 3.8.1. 3.8.2. 3.8.3. 3.8.4. 3.8.5. 3.8.6. 3.8.7. 3.8.8. 3.8.9. 3.8.10. 3.8.11. 3.8.12. 3.8.13. 3.8.14. 3.8.15. 3.8.16. 4 RID – Revision Identification Register – Device #0..................................... 54 SUBC – Sub-Class Code Register – Device #0.......................................... 54 BCC – Base Class Code Register – Device #0........................................... 54 MLT – Master Latency Timer Register – Device #0.................................... 55 HDR – ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) MBASE1 – Memory Base Address Register – Device #1 ........................... 96 MLIMIT1 – Memory Limit Address Register – Device #1............................ 97 PMBASE1 – Prefetchable Memory Base Address Register – Device #1 ... 98 PMLIMIT1 – Prefetchable Memory Limit Address Register – Device #1 .... 99 BCTRL1 – ...
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... MCH-M Target and Initiator Operations for AGP FRAME# Transactions ................................................................................. 120 Various States ........................................................................................... 123 General Description of Supported CPU States ......................................... 123 General Description of ACPI System States ............................................. 124 Power Transitions...................................................................................... 124 ® Intel SpeedStep Technology.................................................................... 125 XOR Test Mode Initialization..................................................................... 143 XOR Chains .............................................................................................. 144 Datasheet R 250687-002 ...
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... R Figures ® Figure 1. Intel 845MP/845MZ Chipset System Block Diagram .............................................. 14 Figure 2. Configuration Address Register ................................................................................ 39 Figure 3. Configuration Data Register...................................................................................... 41 Figure 4. PAM Register Attributes............................................................................................ 66 Figure 5. Addressable Memory Space................................................................................... 105 Figure 6. Detailed DOS Compatible Area Address Map........................................................ 106 Figure 7. Detailed Extended Memory Range Address Map................................................... 108 Figure 8 ...
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... Table 31. PCI Commands Supported by the MCH-M When Acting as a FRAME# Target ... 120 Table 32. Power Management State Combinations .............................................................. 123 Table 33. Intel 845MP/845MZ Power Transitions .................................................................. 124 Table 34. Absolute Maximum Ratings ................................................................................... 126 Table 35. Intel 845MP/845MZ Chipset MCH-M Package Thermal Resistance..................... 126 Table 36. Power Characteristics ............................................................................................ 127 Table 37. Signal Groups ........................................................................................................ 128 Table 38. DC Characteristics ................................................................................................. 130 Table 39 ...
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... R Revision History Rev. 001 Initial release 002 Included 845MZ data 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Description Datasheet Date March 2002 April 2002 9 ...
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... Advanced Configuration and Power Interface Specification (ACPI) Rev. 1.0b ® Note: See Mobile Intel Pentium for an expanded set of related documents. 10 ® 4 Processor-M and Intel 845MP/845MZ Chipset Platform ® ® 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide Datasheet R Document Number/Location www.developer.intel.com www.developer.intel.com www.developer.intel.com www.developer.intel.com www.jedec.org www ...
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... System Bus - Processor-to-MCH-M interface. The Enhanced Mode of the Scalable Bus is the P6 Bus plus enhancements, consisting of source synchronous transfers for address and data, and system bus interrupt delivery. The Mobile Intel Pentium 4 Processor-M implements a subset of Enhanced Mode. Hub interface - The proprietary hub interconnect that ties the MCH-M to the ICH3-M. In this document hub interface cycles originating from or destined for the primary PCI interface on the ICH3-M is generally referred to as hub interface cycles ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Qword (QW) – Quadword: 8bytes = 4 words DQword (DQW) – Double Quadword: 16 bytes or 8 words. This is sometimes referred Superword (SW of Sword), and is also referred “Cache Line”. 12 Datasheet R 250687-002 ...
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... CPU Supports the Intel Pentium the Enhanced Mode Scaleable Bus Protocol 2x Address, 4x Data Mobile Intel Pentium 4 Processor-M System Bus interrupt delivery Supports system bus at 400 MT/s (100 MHz) Supports host bus Dynamic Bus Inversion (DBI) Supports 32-bit host bus addressing ...
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... Primary & Secondary IDE The Intel 845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) is designed for use with the Mobile Intel Pentium 4 Processor-M. The Intel 845MP/845MZ Chipset MCH-M manages the flow of information between its four interfaces: the System Bus, the memory interface, the AGP port, and the hub interface ...
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... The Intel 845MP/845MZ Chipset Memory Controller Hub-M (MCH-M) component provides the processor interface, DRAM interface, AGP interface, and hub interface. The CPU interface supports the Mobile Intel Pentium 4 Processor-M subset of the Extended Mode of the Scalable Bus Protocol. The Intel 845MP/845MZ Chipset is optimized for the Mobile Intel Pentium 4 Processor-M. It supports a single channel of DDR memory ...
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... The memory interface provides optional ECC error checking for DRAM data integrity. During DRAM writes, ECC is generated on a QWORD (64 bit) basis. Because the Intel 845MP/845MZ Chipset MCH- M stores only entire cache lines in its internal buffers, partial QWORD writes initially cause a read of the underlying data, and their write-back into memory is no different from that of a complete cache line ...
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... Mbit Mbit 128 MB 16M x 64 128 Mbit 256 MB 32M x 64 256 Mbit 512 MB 64M x 64 512 Mbit 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) DDR # of Package Organization Components Type lead TSOP lead TSOP ...
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... Chipset-Mobile (MCH-M) 1.4. AGP Interface A single AGP component or connector (not both) is supported by the Intel 845MP/845MZ Chipset MCH-M AGP interface. The AGP buffers operate only in 1.5-V mode. They are not 3.3-V safe. The AGP interface supports 1x/2x/4x AGP signaling and 2x/4x Fast Writes. AGP semantic cycles to DRAM are not snooped on the host bus ...
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... For message based interrupts, system write buffer coherency is maintained by relying on strict ordering of Memory Writes. The Intel 845MP/845MZ Chipset MCH-M ensures that all Memory Writes received from a given interface prior to an interrupt message Memory Write are delivered to the system bus for snooping in the same order that they occur on the given interface ...
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... This must be taken into account and the addresses and data bus signals must be inverted inside the Intel 845MP/845MZ Chipset MCH-M. All processor control signals follow normal convention. A “0” indicates an active level (low voltage) if the signal is followed by “#” symbol, and a “ ...
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... AGTL+ 4x DRDY# HA[31:3]# AGTL+ 2x HADSTB[1:0]# AGTL+ 2x 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Type I/O Address Strobe: The system bus owner asserts ADS# to indicate the first of two AGTL+ cycles of a request phase. I/O Block Next Request: Used to block the current request bus owner from issuing a AGTL+ new request ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name HD[63:0]# AGTL+ 4x HDSTBP[3:0]# AGTL+ 4x HDSTBN[3:0]# HIT# HITM# HLOCK# HREQ[4:0]# AGTL+ 2x HTRDY# RS[2:0]# 22 Type I/O Host Data: These signals are connected to the system data bus. HD[63:0]# are transferred at 4x rate. Note that the data signals are inverted on the system bus. ...
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... RCVENOUT# CMOS RCVENIN# CMOS 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) O Chip Select: These pins select the particular DDR components during the active state. Note: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These signals can be toggled on every rising System Memory Clock edge. ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 2.3. Hub Interface Signals Table 6. Hub Interface Signal Descriptions Signal Name HI_[10:0] CMOS HI_STB CMOS HI_STB# CMOS 2.4. AGP Interface Signals 2.4.1. AGP Addressing Signals Table 7. AGP Addressing Signal Descriptions Signal Name PIPE# SBA[7:0] NOTE: The above table contains two mechanisms, SBA and PIPE#, to queue requests by the AGP master. Note that the master can only use one mechanism ...
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... AGP Status Signals Table 9. AGP Status Signal Descriptions Signal Name ST[2:0] 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Type I Read Buffer Full: Indicates if the master is ready to accept previously requested AGP low priority read data. When RBF# is asserted, the MCH-M is not allowed to initiate the return of low priority read data. That is, the MCH-M can only finish returning the data for the request currently being serviced ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 2.4.4. AGP Strobes Table 10. AGP Strobe Descriptions Signal Name AD_STB0 (s/t/s) AD_STB0# (s/t/s) AD_STB1 (s/t/s) AD_STB1# (s/t/s) SB_STB SB_STB# 26 Type I/O Address/Data Bus Strobe-0: provides timing for 2x and 4x data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. AGP ...
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... Table 11. AGP/PCI Signal Semantics Descriptions Signal Name G_FRAME# G_IRDY# G_TRDY# 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Type I/O G_FRAME: Frame s/t/s During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations. AGP During Fast Write Operation: Used to frame transactions as an output during Fast Writes ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name G_STOP# G_DEVSEL# G_REQ# G_GNT# G_AD[31:0] G_CBE[3:0]# 28 Type I/O G_STOP#: Stop s/t/s During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA AGP operation. During FRAME# Operation: G_STOP input when the MCH-M acts as a FRAME#-based AGP initiator and is an output when the MCH-M acts as a FRAME#-based AGP target ...
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... NOTE: PCIRST# from the ICH3-M is connected to RSTIN# and is used to reset AGP interface logic within the MCH-M. The AGP agent will also use PCIRST# provided by the ICH3 input to reset its internal logic. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Type I/O Parity AGP ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 2.5. Clocks, Reset, and Miscellaneous Table 12. Clocks, Reset, and Miscellaneous Descriptions Signal Name BCLK / BCLK# CMOS 66IN CMOS SCK[5:0] CMOS SCK#[5:0] CMOS RSTIN# CMOS TESTIN# CMOS 30 Type I Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer ...
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... Weak internal pull-up, Weak internal pull down (Strap): Strap input sampled during assertion or on the deassertion edge of RSTIN# 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Type Ref Host Reference Voltage. Reference voltage input for the Data, Address, and Common clock signals of the Host AGTL+ interface Ref DDR Reference Voltage: Reference voltage input for DQ, DQS, & ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Table 14. Host Signals Buffer Signal Type/I Type O HA[31:3]# GTL+ I/O HD[63:0]# GTL+ I/O ADS# GTL+ I/O BNR# GTL+ I/O BPRI# GTL+ O DBSY# GTL+ I/O DEFER# GTL+ O DRDY# GTL+ I/O HIT# GTL+ I/O HITM# GTL+ I/O HLOCK# GTL+ I HREQ[4:0]# GTL+ I/O HTRDY# GTL+ I/O RS[2:0]# GTL+ O CPURST# GTL State ...
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... O SM common SCAS common SMA[12: common SCS#[3: common * There is an indeterminate number of non-CKE DDR pins that will be pull-down in S3. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) State State After C3 During RSTIN# RSTIN# Deassertion Assertion TRI Don’t DRIVE care TRI Don’ ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Table 16. AGP Signals Buffer Signal Type Type IO PIPE# CMOS Input SBA[7:0] CMOS Input RBF# CMOS Input WBF# CMOS Input ST[2:0] CMOS Output AD_STB0 CMOS I/O AD_STB0 CMOS I/O # AD_STB1 CMOS I/O AD_STB1 CMOS I/O # SB_STB CMOS I SB_STB# CMOS I G_FRAM CMOS I/O E# G_IRDY# ...
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... RSTIN# CMOS I GRCOMP CMOS I/O HLRCOMP CMOS I/O Table 18. Hub Interface Signals Buffer Signal Type/I Type O HI_STB CMOS I/O HI_STB# CMOS I/O HI_[10:0] CMOS I/O 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) State State After C3 During RSTIN# RSTIN# Deassertion Assertion IN IN Running N/A N/A Running Tri N/A Hi-Z Tri N/A Hi-Z State ...
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... DRAM Controller/8 bit HI_A Controller Host-to-AGP Bridge (virtual P2P) NOTE: A physical PCI bus #0 does not exist. The hub interface and the internal devices in the Intel 845MP/845MZ Chipset MCH-M and ICH3-M logically constitute PCI Bus #0 to configuration software. 3.2. Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based " ...
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... Configuration Cycle. The ICH3-M compares the non-zero Bus Number with the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the configuration cycle is meant for Primary PCI or a downstream PCI bus. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Datasheet 37 ...
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... Note the software does not need to perform read, merge, and write operation for the configuration address register. Reserved Registers: In addition to reserved bits within a register, the MCH-M contains address locations in the configuration space of the Host-HI Bridge entity that are marked either "Reserved" or “Intel Reserved”. When a 38 Datasheet R ...
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... R “Reserved” register location is read, a random value is returned. (“Reserved” registers can be 8-bit, 16- bit, or 32-bit in size.) Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. Default Value Upon Reset: Upon a full Reset, the MCH-M sets all of its internal configuration registers to predetermined default states ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Bit 31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI configuration space are enabled. If this bit is reset to 0, accesses to PCI configuration space are disabled. 30:24 Reserved (These bits are read only and have a value of 0). 23:16 Bus Number: When the Bus Number is programmed to 00h the target of the Configuration Cycle is a hub interface agent (MCH-M, ICH3-M, etc ...
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... Figure 3. Configuration Data Register 31 Configuration Data Window Bit 31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1 any I/O access that to the CONFIG_DATA register will be mapped to configuration space using the contents of CONFIG_ADDRESS. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 0CFCh 00000000h Read/Write 32 bits 0 Descriptions Datasheet 0 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.6. Memory Mapped Register Space All System Memory control functions have been consolidated into a new memory mapped address region within Device 0 Function 0. This space will be accessed using a new Base Address Register (BAR) located at Dev 0 Func 0 (Offset 14h). By default this BAR will be invisible (i.e., Read-Only zeros). ...
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... Note: Since there are multiple clock signals assigned to each row of a DIMM important to clarify exactly which row width field affects which clock signal. Row Parameters 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 2Ch 00h R/W 8 bits Descriptions DDR Clocks Affected SCK[2:0]/SCK[2:0]# ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.6.2. DQCMDSTR – Strength Control Register for DQ and CMD Signal Groups Address Offset: Default Value: Access: Size: This register controls the drive strength of the I/O buffers for the DQ/DQS and CMD signal groups. Bit 7 Reserved CMD Strength Control (RAS#, CAS#, WE#, MA[12:0], BS[1:0]) 6:4 000 = 0 ...
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... X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4. Reserved. CKE x8 Strength Control: Sets drive strength as shown below: 2:0 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 31h 00h Read Only, Read/Write 8 bits Descriptions Datasheet 45 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.6.4. CSBSTR – Strength Control Register for CS# Signal Group Address Offset: Default Value: Access: Size: This register controls the drive strength of the I/O buffers for the CS# signal group. This group has two possible loadings depending on the width of SDRAM devices used in each Row of memory (x8 or x16). ...
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... X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4. Reserved CK x8 Strength Control: Sets drive strength as shown below: 2:0 000 = 0.75 X (default) 001 = 1.00 X 010 = 1.25 X 011 = 1.50 X 100 = 2.00 X 101 = 2.50 X 110 = 3.00 X 111 = 4.00 X 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 33h 00h Read Only, Read/Write 8 bits Descriptions Datasheet 47 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.6.6. RCVENSTR – Strength Control Register for RCVENOUT# Signals Address Offset: Default Value: Access: Size: This register controls the drive strength of the I/O buffers for the Receive Enable Out (RCVENOUT#) signal. Bit 7:3 Reserved RCVEnOut# Strength Control: Sets drive strength as shown below: 2:0 000 = 0 ...
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... DERRSYN 87-8Bh 8C-8Fh EAP 90-96h PAM[0:6] 97h FDHC 98-9Ch 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Register Name Vendor Identification Device Identification PCI Command Register PCI Status Register Revision Identification Reserved. Sub-Class Code Base Class Code Master Latency Timer Header Type Reserved ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Address Register Offset Symbol 9Dh SMRAM 9Eh ESMRAMC 9Fh A0-A3h ACAPID A4-A7h AGPSTAT A8-Abh AGPCMD AC-Afh B0-B3h AGPCTRL B4h APSIZE B5-B7h B8-BBh ATTBASE BCh AMTT BDh LPTT BE-C3h C4-C5h TOM C6-C7h MCHCFG C8-C9h ERRSTS CA-CBh ERRCMD ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.7.2. DID – Device Identification Register – Device#0 Address Offset: ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.3. PCICMD – PCI Command Register – Device #0 Address Offset: Default: Access: Size Since MCH-M Device #0 does not physically reside on PCI0 many of the bits are not implemented Bit 15:10 Reserved 9 Fast Back-to-Back Enable (RO). This bit controls whether or not the master can do fast back-to- back writes to different targets ...
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... CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the AGP Capability standard register resides. 3:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 06-07h 0090h Read Only, Read/Write Clear 16 bits Description Datasheet ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.5. RID – Revision Identification Register – Device #0 Address Offset: Default Value: Access: Size: This register contains the revision number of the MCH-M Device #0. These bits are read only and writes to this register have no effect. Bit 7:0 Revision Identification Number. This is an 8-bit value that indicates the revision identification number for the MCH-M Device #0 ...
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... Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 This read only field always returns 0 when read and writes have no effect. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 0Dh 00h Read Only 8 bits Description 0Eh ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.10. APBASE – Aperture Base Configuration Register – Device #0 Offset: Default: Access: Size: The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to “ ...
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... The CAPPTR provides the offset that is the pointer to the location where the AGP standard registers are located. Bit 7:0 Pointer to the start of AGP standard register block. This pointer tells software where it can find the beginning of the AGP register block. The value in this field is E4h. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 2C-2Dh 0000h Read/Write Once 16 bits Description 2E-2Fh ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.14. AGPM- AGP Miscellaneous Configuration Offset: Default: Access: Size: Bit 7:2 Reserved 1 Aperture Access Global Enable (APEN): This bit is used to prevent access to the graphics aperture from any port (CPU, HI_A, or AGP/PCI_B) before the aperture range is established by the configuration software and the appropriate translation table in the main DRAM has been initialized. ...
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... Row Attribute for even-numbered row: This 3-bit field defines the page size of the corresponding row. 001 010 011 100 Others: Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 70-73h 00h Read/Write 8 bits Row Attribute for Row0 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.17. DRT – DRAM Timing Register – Device #0 Offset: Default: Access: Size: Bit 31:19 Reserved 18:16 DRAM Idle Timer: This field determines the number of clocks the DRAM controller will remain in the idle state before it begins precharging all pages. 000 ...
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... Refresh Mode Select (RMS): This field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 000: 001: 010: 011: 111: Other: 7 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 7C-7Fh 00000000h Read/Write 32 bits Description All rows allowed the active state Reserved. Non-ECC mode Error checking with correction. Reserved Refresh disabled Refresh enabled. Refresh interval 15.6 µ ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Bit 6:4 Mode Select (SMS). These bits select the special operational mode of the DRAM interface. The special modes are intended for initialization at power up. 000: Post Reset state – When the MCH-M exits reset (power-up or otherwise), the mode select field is cleared to “ ...
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... Once the error flag bits are set as a result of an error, this bit field is locked and doesn’t change as a result of a new error. 0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 86h 00hb Read Only 8 bits ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.21. PAM[0:6] – Programmable Attribute Map Registers – Device #0 Address Offset: Default Value: Attribute: Size: The MCH-M allows programmable memory attributes on 13 Legacy memory segments of various sizes in the 640 Kbytes to 1 Mbytes address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features ...
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... After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. Figure 4 and Table 23 show the PAM registers and the associated attribute bits: 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Bits [5, 1] Bits [ ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Figure 4. PAM Register Attributes Reserved 66 PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 Reserved Write Enable (R/W) 1=Enable 0=Disable Read Enable (R/W) 1=Enable Reserved 0=Disable Datasheet Offset 96h 95h 94h 93h 92h 91h ...
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... AGP. Expansion Area (C0000h-DFFFFh) This 128-KB area is divided into eight 16-KB segments, which can be assigned with different attributes via PAM control register as defined by above. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Attribute Bits Memory Segment Reserved R ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Extended System BIOS Area (E0000h-EFFFFh) This 64-Kbytes area is divided into four 16-Kbytes segments which can be assigned with different attributes via PAM control register as defined by the table above. System BIOS Area (F0000h-FFFFFh) This area is a single 64-Kbytes segment, which can be assigned with different attributes via PAM control register as defined by the table above ...
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... SMM space. “SMM DRAM” is not remapped simply “made visible” if the conditions are right to access SMM space, otherwise the access is forwarded to the hub interface. C_BASE_SEG is hardwired to 010 to indicate that the MCH-M supports the SMM space at A0000h-BFFFFh. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 9Dh 02h Read/Write, Read Only, Lock ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.24. ESMRAMC – Extended System Mgmt RAM Control Register – Device #0 Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MByte ...
Page 71
... AGP Capability ID (CAPID): This field identifies the linked list item as containing AGP registers. This field has a value of 0000_0010b assigned by the PCI SIG. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) A0-A3h 0020_0002h Read Only 32 bits Description ...
Page 72
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.26. AGPSTAT – AGP Status Register – Device #0 Address Offset: Default Value: Access: Size: This register reports AGP device capability/status. Bit 31:24 Request Queue (RQ): This field is hardwired to 1Fh to indicate a maximum of 32 outstanding AGP command requests can be handled by the MCH-M. This field contains the maximum number of AGP command requests the MCH-M is configured to manage ...
Page 73
... AGP master (after that capability has been verified by accessing the same functional register within the AGP masters’ configuration space.) NOTE: This field applies to G_AD and SBA buses. It also applies to Fast Writes if they are enabled. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) A8-ABh 0000_0000h Read/Write, Read Only ...
Page 74
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.28. AGPCTRL – AGP Control Register Address Offset: Default Value: Access: Size: This register provides for additional control of the AGP interface. Bit 31:8 Reserved 7 GTLB Enable (and GTLB Flush Control) (R/W): When this bit is set, it enables normal operations of the Graphics Translation Lookaside Buffer zero, the GTLB is flushed by clearing the valid bits associated with each entry ...
Page 75
... Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e. all bits respond as “hardwired” to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) B4h 00h Read/Write, Read Only 8 bits ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.30. ATTBASE – Aperture Translation Table Base Register – Device #0 Address Offset: Default Value: Access: Size: This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DRAM. This value is used by the MCH-M Graphics Aperture address translation logic (including the GTLB logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical DRAM address ...
Page 77
... AGP master or MCH-M) after which the AGP arbiter may grant the bus to another agent. 2:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) BCh 00h Read/Write, Read Only 8 bits ...
Page 78
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.32. LPTT – AGP Low Priority Transaction Timer Register – Device #0 Address Offset: Default Value: Access: Size: LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SBA mechanisms ...
Page 79
... PCI memory or the graphics aperture, whichever is smaller. Programming example: 400h = 1 GB. An access to 4000_0000h or above will be considered above the TOM and therefore not routed to DRAM. It may go to AGP, aperture, or subtractively decode to Hub Interface. 3:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) C4-C5h 0100h Read/Write 16 bits Description Datasheet ...
Page 80
... Bit 15:12 Reserved 11 System Memory Frequency Select: This bit must be programmed prior to memory initialization. This bit must be programmed/set to “0” prior to memory initialization in order to guarantee proper operation of the Intel®845MZ 10:6 Reserved 5 Monochrome Display adapter Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of device 1 to control the routing of host initiated transactions targeting MDA compatible I/O and memory address ranges ...
Page 81
... Once this bit is set the EAP, CN, DN, and ES fields are locked to further single bit error updates until the processor clears this bit by writing a 1. Software must write a “1” to clear this bit and unlock the error logging mechanism. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) C8-C9h 0000h Read Only, Read/Write Clear ...
Page 82
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.36. ERRCMD – Error Command Register – Device #0 Address Offset: Default Value: Access: Size: This register enables various errors to generate an SERR message via the hub interface A. Since the MCH-M does not have an SERR# signal, SERR messages are passed from the MCH-M to the ICH3-M over the hub interface ...
Page 83
... SCI on Single-bit ECC Error (DSERR): When this bit is set, the generation of the hub interface A SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems that do not support ECC this bit must be disabled. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) CC-CDh 0000h Read/Write, Read Only ...
Page 84
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.7.39. SKPD – Scratchpad Data – Device #0 Address Offset: Default Value: Access: Size: Bit 15:0 Scratchpad [15:0]. These bits are simply R/W storage bits that have no affect on the MCH-M functionality. 3.7.40. CAPID – Product Specific Capability Identifier Address Offset: Default Value: ...
Page 85
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Register Symbol Register Name VID1 Vendor Identification DID1 Device Identification PCICMD1 PCI Command Register PCISTS1 PCI Status Register RID1 Revision Identification Reserved ...
Page 86
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Address Offset 26-27h 28-3Dh 3Eh 3Fh 40h 41h-4Fh 50-57h 58-5Fh 59-FFh 86 Register Symbol Register Name PMLIMIT1 Prefetchable Memory Limit Address Reg. Reserved BCTRL1 Bridge Control Register Reserved ERRCMD1 Error Command Reserved DWTMC DRAM Write Thermal Mgnt. Control DRTMC DRAM Read Thermal Mgnt ...
Page 87
... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. 3.8.2. DID1 – Device Identification Register – Device #1 Address Offset: ...
Page 88
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.3. PCICMD1 – PCI-PCI Command Register – Device #1 Address Offset: Default: Access: Size Bit 15:10 Reserved 9 Fast Back-to-Back Enable (FB2BEn): Not Applicable. Hardwired to “0.” 8 SERR Message Enable (SERRE1): This bit is a global enable bit for Device #1 SERR messaging. ...
Page 89
... Reserved 5 66-MHz Capability (CAP66): This bit is hardwired to “1” to indicate that the AGP port is 66-MHz capable. 4:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 06-07h 00A0h Read Only, Read/Write Clear 16 bits Descriptions Datasheet 89 ...
Page 90
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.5. RID1 – Revision Identification Register – Device #1 Address Offset: Default Value: Access: Size: This register contains the revision number of the MCH-M device #1. These bits are read only and writes to this register have no effect. For the A-0 stepping, this value is 00h. ...
Page 91
... Offset: Default: Access: Size: This register identifies the header layout of the configuration space. Bit 7:0 This read only field always returns 01h when read. Writes have no effect. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 0Bh 06h Read Only 8 bits Description 0Dh 00h Read/Write ...
Page 92
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.10. PBUSN1 – Primary Bus Number Register – Device #1 Offset: Default: Access: Size: This register identifies that “virtual” PCI-PCI Bridge is connected to bus #0. Bit 7:0 Bus Number. Hardwired to “0.” 3.8.11. SBUSN1 – Secondary Bus Number Register – Device #1 ...
Page 93
... When the SMLT1 is disabled, the burst time for the MCH-M is unlimited (i.e. the MCH-M can burst forever). Bit 7:3 Secondary MLT counter value. Default=0, i.e. SMLT1 disabled 2:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 1Bh 00h Read/Write, Read Only 8 bits Description Datasheet 93 ...
Page 94
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.14. IOBASE1 – I/O Base Address Register – Device #1 Address Offset: Default Value: Access: Size: This register controls the hosts to AGP I/O access routing based on the following formula: IO_BASE=< address =<IO_LIMIT Only the upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated as 0 ...
Page 95
... AGP interface. 6 Reserved 5 66 MHz Capable (CAP66): This bit is hardwired indicate that AGP bus is capable of 66-MHz operation. 4:0 Reserved 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 1E-1Fh 02A0h Read Only, Read/Write Clear 16 bits Descriptions Datasheet 95 ...
Page 96
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.17. MBASE1 – Memory Base Address Register – Device #1 Address Offset: Default Value: Access: Size: This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula: MEMORY_BASE1=< address =<MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address ...
Page 97
... PMBASE 1and PMLIMIT1 are used to map prefetchable address ranges (typically graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP memory access performance. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 22-23h 0000h Read/Write, Read Only 16 bits ...
Page 98
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.19. PMBASE1 – Prefetchable Memory Base Address Register – Device #1 Address Offset: Default Value: Access: Size: This register controls the host to AGP prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE1=< address =<PREFETCHABLE_MEMORY_LIMIT1 The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address ...
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... Note: Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e. prefetchable) from the processor perspective. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 26-27h 0000h Read/Write, Read Only ...
Page 100
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.21. BCTRL1 – PCI-PCI Bridge Control Register – Device #1 Address Offset: Default: Access: Size This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e. AGP) as well as some bits that affect the overall behavior of the “ ...
Page 101
... A upon receiving a target abort on AGP. When this bit is set to 0, the MCH-M does not assert an SERR message upon receipt of a target abort on AGP. SERR messaging for Device 1 is globally enabled in the PCICMD1 register. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 40h 00h Read/Write, Read Only ...
Page 102
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.23. DWTMC – DRAM Write Thermal Management Control Offset: Default: Access: Size: Bit 63:52 Reserved 51:50 TM Lock: These bits secure the DRAM Thermal Management control registers. The bits default to ‘0’. Once a ‘1’ is written to either bit, the configuration register bits specified in DWTMC and DRTMC ...
Page 103
... When this bit is reset to ‘0’, write thermal management stops and the counters associated with WTMW and WTHM are reset. Software writes to this bit to start and stop write thermal management. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Thermal management via Counters and Hardware Thermal Management_on signal mechanisms disabled. ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 3.8.24. DRTMC – DRAM Read Thermal Management Control Offset: Default: Access: Size: Bit 63:49 Reserved 48:41 Global DRAM Read Sampling Window (GDRSW): This eight bit value is multiplied by 4*10 define the length of time in host clocks over which the number of hexwords read from the DRAM is counted ...
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... R 4. System Address Map A system based on the Intel 845MP/845MZ Chipset supports addressable memory space and 64 KB+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O regions are used solely to control the operation of devices in the system ...
Page 106
... VGAEN bit (but accesses to the VGAA and VGAB ranges will still be sent to AGP). Legacy support requires the ability to have a second graphics controller (monochrome) in the system Intel 845MP/845MZ Chipset system, accesses in the standard VGA range are forwarded to AGP when VGAEN is set. Since the monochrome adapter may be on the hub interface bus (or other expansion bus), the MCH-M must be able to decode cycles in the MDA range and forward them to the hub interface ...
Page 107
... The system BIOS region is a single 64-Kbytes segment. This segment can be assigned read and write attributes default (after reset) Read/Write disabled and cycles are forwarded to hub interface. By manipulating the read/write attributes, the MCH-M can “shadow” BIOS into main DRAM. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) From 0_000C_0000 0_000C_4000 ...
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... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 4.1.3. ISA Hole Memory Space BIOS software may optionally open a “window” between 15 MB and 16 MB (0_00F0_0000h to 0_00FF_FFFF) that relays transactions to hub interface instead of completing them with a system memory access. This window is opened with the FDHC.HEN configuration field. ...
Page 109
... DRAM memory and is defined by the APBASE and APSIZE configuration registers of the Intel 845MP/845MZ Chipset MCH-M. Note that the AGP aperture must be above the top of memory and must not intersect with any other address space. ...
Page 110
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) 4.1.9. Hub Interface A Subtractive Decode HLA_SUB All accesses that fall between the value programmed into the TOM register and 4GB are subtractively decoded and forwarded to hub interface if they do not decode to a space that corresponds to another device. 4.2. AGP Memory Address Ranges The MCH-M can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in MCH-M Device #1 configuration space ...
Page 111
... MB to allow for simpler decoding and the TSEG was remapped to just under the TOM. In the MCH-M 256 MB do not offset the TSEG region and it is not remapped. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Transaction Address Space (Adr) DRAM Space (DRAM) ...
Page 112
... I/O Address Space The Intel 845MP/845MZ Chipset MCH-M does not support the existence of any other I/O devices beside itself on the system bus. The MCH-M generates either hub interface A or AGP bus cycles for all processor I/O accesses. The MCH-M contains two internal registers in the processor I/O space, Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) ...
Page 113
... AGP PIPE# and SBA accesses are limited to 256 bytes and must hit DRAM. Read accesses crossing out of DRAM will return invalid data, and the IAAF Error bit will be set. Write accesses crossing out of DRAM will be discarded, and the IAAF Error bit will be set. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Datasheet 113 ...
Page 114
... System Bus Interrupt Delivery The Mobile Intel Pentium 4 Processor-M supports System Bus interrupt delivery, but they do not support the APIC serial bus interrupt delivery mechanism. Interrupt related messages are encoded on the System Bus as “Interrupt Message Transactions” Intel 845MP/845MZ Chipset platform, System Bus interrupts may originate from the processor on the System Bus, or from a downstream device on hub interface, or AGP. In the later case the MCH-M drives the “ ...
Page 115
... System Memory Interface 5.2.1. DDR Interface Overview The Intel 845MP Chipset MCH-M supports DDR at 200 and 266 MHz and includes support for: • PC2100 DDR • PC2100, unbuffered, 200-pin DDR SO-DIMMs • Maximum of 2 SO-DIMMs, Single-sided and/or Double-sided b • Configurable optional ECC The Intel 845MZ Chipset MCH-M supports DDR at 200 MHz and includes support for: • ...
Page 116
... System Management Bus on the ICH3-M. Thus, data is read from the Serial Presence Detect port on the SO-DIMMs via a series of IO cycles to the south bridge. BIOS essentially needs to determine the size and type of memory used for each of the rows of memory in order to properly configure the Intel 845MP/845MZ MCH-M memory interface. ...
Page 117
... MCH-M performs two Qword writes at a time so two 8-bit codes are sent with each write. Since the code word covers a full Qword, writes of less than a Qword require a read-merge-write operation. Consider a Dword write to memory. In this case, when in ECC mode, the Intel 845MP/845MZ MCH-M will read the Qword where the addressed Dword will be written, merge in the new Dword, generate a code covering the new Qword and finally write the entire Qword and code back to memory ...
Page 118
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) AGP PIPE# or SBA[7:0] protocol transactions to DRAM do not get snooped and are, therefore, not coherent with the processor caches. AGP FRAME# protocol transactions to DRAM are snooped. AGP PIPE# and SBA[7:0] accesses to and from the hub interface are not supported. AGP FRAME# access from an AGP master to the hub interface are also not supported ...
Page 119
... The MCH-M will not generate Fast Back to Back (FB2B) cycles in 1x mode, but will generate FB2B cycles in 2x and 4x Fast Write modes. To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4 of the AGP Command Register), must be set to 1. 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Cycle Destination 1111 N/A No Response ...
Page 120
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Memory writes originating from the host or from the hub interface use the Fast Write protocol when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is dependent on the bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4x strobing ...
Page 121
... I/O Read and Write. I/O reads and writes from the host are sent to the AGP bus if they fall within the I/O base and limit address range for the AGP bus as programmed in the MCH-M’s PCI configuration registers. All other host-initiated I/O accesses that do not correspond to this 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) C/BE[3:0]# Encoding Cycle Destination 1001 ...
Page 122
... The MCH-M generates a Delayed Transaction on the AGP only for AGP FRAME# to DRAM read accesses. The MCH-M does not allow more than one Delayed Transaction access from AGP at any time. 5.4. Power and Thermal Management An Intel 845MP/845MZ Chipset platform is compliant with the following specifications: • APM Rev 1.2 • ACPI Rev 1.0b • ACPI Rev 2.0 • ...
Page 123
... AGP, AGP/PCI, or HubLink cycles (except special cycles) will occur while the MCH this state. The processor cannot snoop its caches to maintain coherency while in the C3 state. • C4 (DeepER Sleep): The C4 state appears to Intel 845MP/845MZ as identical to the C3 state, but in this state the processor core voltage is lowered. There are no internal events in Intel 845MP/845MZ for the C4 state that differ from the C3 state ...
Page 124
... S1-M (Powered on Suspend for Mobile Systems): Power is maintained to the CPU and all system components, but most clocks are stopped by the clock synthesizer. • S2: ACPI S2 state is not supported in the Intel 845MP/845MZ Chipset platform. • S3 (Suspend To RAM): The next level of power reduction occurs when the clock synthesizer and core well power planes for the processor and chipset are shut down, but the main memory power plane and the ICH3-M resume well remain active ...
Page 125
... CPU PLL multiplier, which can only be done in the Deep Sleep CPU state (clock going to the CPU is stopped), which is the C3 CPU power state. Most of the control for Intel SpeedStep technology is done in the ICH3-M. However, the MCH-M must cooperate on certain functions. ...
Page 126
... Voltage on 2.5 V DDR tolerant input pins with IL, IH (DDR) respect to Vss 6.2. Thermal Characteristics The Intel 845MP/845MZ Chipset MCH-M is designed for operation at die temperatures between 0°C and 104°C. The thermal resistance of the package is given in Table 35. Table 35. Intel 845MP/845MZ Chipset MCH-M Package Thermal Resistance Parameter Ψ (°C/Watt)** jt Θ ...
Page 127
... It does not represent the expected power generated by a power virus. Studies by Intel indicate that no application will cause thermally significant power dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads that write but never read. ...
Page 128
... The signal description includes the type of buffer used for the particular signal. AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The Intel 845MP/845MZ Chipset MCH-M integrates most AGTL+ termination resistors. AGP AGP interface signals. These signals are compatible with AGP 2.0 1.5 V Signaling Environment DC and AC Specifications ...
Page 129
... Clocks, Reset, and Miscellaneous Signal Groups (o) (p) (q) (v) I/O Buffer Supply Voltages (r) (s) (t) (u) 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Type DDR CMOS I/O SDQ[63:0], SCB[7:0], SDQS[8:0] DDR CMOS SCS[3:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, Output SWE#, SCKE[3:0], RCVENOUT#, SCK[5:0], SCK[5:0]# DDR CMOS Input RCVENIN# ...
Page 130
... Intel 82845MP/82845MZ Chipset-Mobile (MCH- Characteristics Table 38. DC Characteristics Symbol Signal Group I/O Buffer Supply Voltage VCCSM (u) DDR I/O Supply Voltage VCC1_8 (t) 1.8V I/O Supply Voltage VCC1_5 (s) Core and AGP Voltage VTT (r) Host AGTL+ Termination Voltage VTTactive (r) BK-M Active Range VTTsleep ® BK-M Inactive Range Reference Voltages ...
Page 131
... Hub Interface Output Low OL_HI Current I (i) Hub Interface Output High OH_HI Current I (i) Hub Interface Input LEAK_HI Leakage Current C (i) Hub Interface Input IN_HI Capacitance 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Parameter Min Nom SDREF + 0.15 SDREF + 0.31 1.80 -9.375 16 4.690 0.6 x VCC1_5 0.85 x VCC1_5 -0.2 1.32 HIREF + 0.15 0.9 x VCC1_8 -1 2.58 Datasheet ...
Page 132
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Symbol Signal Group Miscellaneous Signals V (o) Input Low Voltage IL V (o) Input High Voltage IH V (o) Output Low Voltage OL V (o) Output High Voltage OH I (o) Output Low Current OL I (o) Output High Current OH I (o) Input Leakage Current LEAK C (o) Input Capacitance ...
Page 133
... E VSS SDQ3 SDQ8 VSS D SDQ13 SDQ14 C VCCSM SDQ2 SDQ9 SDQS1 B SDQ7 SDQ12 A VSS 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH- VCC1_5 VTT VTT G_GNT# VSS VSS ST0 G_REQ# VTT VSS VTT VSS ST1 VCC1_5 PIPE# VSS SBA7 SBA6 ...
Page 134
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Table 40. Top View (Right Side VSS VSS VSS HD57# HD49# HD44# HD54# HD52# HD48# HD45# HD42# VSS HD51# VSS HD47# VSS HD60# HD53# HD46# HD40# HDSTBN2# HD36# HSWNG DBI3# VSS VSS HDSTBP2# 1 HRCOM HDSTBN3# ...
Page 135
... R25 G_AD4 T26 G_AD5 T27 G_AD6 U27 G_AD7 U28 G_AD8 V26 G_AD9 V27 G_AD10 T23 G_AD11 U23 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name Ball # G_AD12 T24 G_AD13 U24 G_AD14 U25 G_AD15 V24 G_AD16 Y27 G_AD17 Y26 G_AD18 AA28 G_AD19 ...
Page 136
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name Ball # HD0# AA2 HD1# AB5 HD2# AA5 HD3# AB3 HD4# AB4 HD5# AC5 HD6# AA3 HD7# AA6 HD8# AE3 HD9# AB7 HD10# AD7 HD11# AC7 HD12# AC6 HD13# AC3 HD14# AC8 HD15# AE2 HD16# ...
Page 137
... G14 SCK#4 G24 SCK#5 F5 SCKE0 G23 SCKE1 E22 SCKE2 H23 SCKE3 F23 SCS#0 E9 SCS#1 F7 SCS#2 F9 250687-002 ® Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name Ball # SCS#3 E7 SDQ0 G28 SDQ1 F27 SDQ2 C28 SDQ3 E28 SDQ4 H25 SDQ5 G27 SDQ6 F25 SDQ7 B28 ...
Page 138
... Intel 82845MP/82845MZ Chipset-Mobile (MCH-M) Signal Name Ball # SCB7 D14 SDQS0 F26 SDQS1 C26 SDQS2 C23 SDQS3 B19 SDQS4 D12 SDQS5 C8 SDQS6 C5 SDQS7 E3 SDQS8 E15 SDREF J9,J21 SMA0 E12 SMA1 F17 SMA2 E16 SMA3 G18 SMA4 G19 SMA5 E18 SMA6 F19 ...
Page 139
... R 9.3. Package Mechanical Information Figure 8. MCH-M BGA Package Dimensions (Top View) 250687-001 ® Intel 845MZ Chipset:82845MZ(MCH-M) Datasheet 139 ...
Page 140
... Intel 845MZ Chipset:82845MZ (MCH-M) Figure 9. MCH-M BGA Package Dimensions (Side View) 140 Datasheet R 250687-002 ...
Page 141
... R Figure 10. MCH-M BGA Package Dimensions (Bottom View) 250687-001 ® Intel 845MZ Chipset:82845MZ (MCH-M) Datasheet 141 ...
Page 142
... Intel 845MZ Chipset:82845MZ (MCH-M) Figure 13. FCBGA Handling Zone Description Table 41. FCBGA Handling Zone Description Handling Zone Description Substrate Edges Substrate Corners 142 Handling Area Capacitor Area Value 37 37 Datasheet R Label Ax, Ay Bx, By 250687-002 ...
Page 143
... RSTINB. The signals that need to be pulled are as follows: GGNTB = 0 (Global strap enable) SBA[ (XOR strap) ST[ (PLL Bypass mode recommended to enter PLL Bypass in XOR test mode) 250687-001 Input Input Datasheet ® Intel 845MZ Chipset:82845MZ (MCH-M) Input Input XOR Out xor.vsd 143 ...
Page 144
... Intel 845MZ Chipset:82845MZ (MCH-M) 9.4.2. XOR Chains Table 42. XOR Chains Chain 0 Ball Element # AE6 AD3 144 DDR Signal Name Note 1 HDSTBP1# Input 2 HDSTBP0# Input 3 ADS# Input ...
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... Input SDQS7 Input SCK#2 Input SDQ56 Input SDQ55 Input SCS#1 Input SDQ50 Input SDQ54 Input SDQS6 Input SDQ52 Input SDQ49 Input Datasheet ® Intel 845MZ Chipset:82845MZ (MCH-M) Initial Logic Level N/A Initial Logic Level ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 1 Ball Element # E10 E11 AH27 34 146 DDR Ball Name Note Initial Logic Level SDQ51 Input 1 SDQ48 Input 1 SDQ53 Input 1 SDQ47 Input 1 SDQ46 Input 1 SDQ43 ...
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... F19 22 G18 23 G20 24 G19 25 F21 26 G21 27 E22 28 G24 29 G23 30 G25 31 H23 32 J25 33 AG28 34 250687-001 ® Intel DDR Ball Name Note Initial Logic Level SDQ39 Input 1 SDQ35 Input 1 SDQ38 Input 1 SCS#2 Input 1 SDQ34 Input 1 SDQ36 Input 1 SWE# Input 1 SDQ33 Input 1 SRAS# Input ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 3 Ball Element # G10 1 G12 2 G15 3 F13 4 C14 5 E14 6 D14 7 C15 8 G17 9 C16 10 D16 11 B15 12 C17 13 B17 14 D18 15 E17 16 B19 17 C18 18 E19 19 C19 20 C20 21 D20 22 C21 23 E20 24 B21 25 E21 26 C22 27 D22 28 C24 29 C23 30 B23 31 D24 32 G22 ...
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... R Chain 3 Ball Element # C27 37 D27 38 B27 39 C26 40 F23 41 E24 42 E25 43 E27 44 N24 45 R24 46 AG27 47 250687-001 ® Intel DDR Ball Name Note Initial Logic Level SDQ9 Input 1 SDQ13 Input 1 SDQ12 Input 1 SDQS1 Input 1 SCKE3 Input 1 SCK4 Input 1 SDQ15 Input 1 SDQ8 Input 1 HL_STB# ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 4 Ball Element # D26 1 F25 2 B28 3 C28 4 E28 5 J24 6 F26 7 H25 8 K25 9 J23 10 F27 11 K23 12 G28 13 G27 14 M27 15 M24 16 N28 17 L28 18 M25 19 N27 20 M26 21 N25 22 L27 23 P25 24 P23 25 P24 26 R27 27 R28 28 U27 29 R25 30 T27 31 T36 32 U28 ...
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... R Chain 4 Ball Element # U27 37 T24 38 U24 39 U25 40 T23 41 V24 42 U23 43 AE28 44 250687-001 ® Intel DDR Ball Name Note Initial Logic Level G_AD8 Input 1 G_AD12 Input 1 G_AD13 Input 1 G_AD14 Input 1 G_AD10 Input 1 G_AD15 Input 1 G_AD11 Input 1 SBA4 Output N/A Datasheet 845MZ Chipset:82845MZ (MCH-M) ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 5 Ball Element # V25 1 W28 2 W25 3 Y25 4 W27 5 V23 6 Y24 7 W24 8 AE23 9 W23 10 AA23 11 AA28 12 Y26 13 Y27 14 AB27 15 AB26 16 AA25 17 AA24 18 AA27 19 AC27 20 Y23 21 AC25 22 AB25 23 AB23 24 AB24 25 AC24 26 AC22 27 AB24 28 AE22 29 AF24 30 AF22 31 AF27 32 AH25 ...
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... R Chain 5 Ball Element # AH17 37 AG16 38 AG17 39 AC16 40 AE11 41 AE27 42 250687-001 ® Intel DDR Ball Name Note Initial Logic Level HD61# Input 1 HD55# Input 1 HD56# Input 1 HDSTBP3# Input 1 HDSTBP2# Input 1 SBA5 Output N/A Datasheet 845MZ Chipset:82845MZ (MCH-M) 153 ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 6 Ball Element # AC27 1 AF27 2 AE17 3 AD17 4 AE16 5 AH15 6 AG15 7 AF16 8 AC16 9 AE15 10 AG14 11 AC17 12 AF14 13 AE14 14 AH13 15 AD15 16 AG13 17 AC14 18 AF12 19 AG12 20 AE12 21 AE13 22 AH9 23 AG10 24 AH11 25 AG9 26 AG11 27 AE11 28 AF10 29 AE10 30 AC12 31 AC11 32 AC10 ...
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... R Chain 6 Ball Element # AH7 37 AH5 38 AG8 AE24 42 250687-001 ® Intel DDR Ball Name Note Initial Logic Level HD24# Input 1 HD31# Input 1 HD27# Input 1 DEFER# Input 1 RS1# Input 1 SBA6 Output N/A Datasheet 845MZ Chipset:82845MZ (MCH-M) 155 ...
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... Intel 845MZ Chipset:82845MZ (MCH-M) Chain 7 Ball Element # AG6 1 AG5 2 AG7 3 AF6 4 AF8 5 AE6 6 AG4 7 AH3 8 AE8 9 AG2 10 AF4 11 AH2 12 AE5 13 AG3 14 AF3 15 AD7 16 AC7 17 AC8 18 AD5 19 AC6 20 AE2 21 AB7 22 AE3 23 AD4 24 AC3 25 AB5 26 AC5 27 AA6 28 AA5 29 AB3 30 AA3 31 AB4 32 AA2 ...
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... AE25 45 NOTE: RSTINB, TESTINB, all Rcomp buffers are not part of any XOR chain. 250687-001 ® Intel DDR Ball Name Note Initial Logic Level HITM# Input HTRDY# Input HLOCK# Input BR0# Input BNR# Input RS0# Input DBSY# ...