CDP1881C Intersil Corporation, CDP1881C Datasheet

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CDP1881C

Manufacturer Part Number
CDP1881C
Description
CMOS 6-Bit Latch and Decoder Memory Interfaces
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CDP1881CE
Manufacturer:
ON
Quantity:
430
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Performs Memory Address Latch and Decoder
• Decodes Up to 16K Bytes of Memory
• Interfaces Directly with CDP1800-Series Microproces-
• Can Replace CDP1866 and CDP1867 (Upward Speed
Ordering Information
Pinouts
PDIP
PDIP
PDIP
SBDIP
PACKAGE
Functions Multiplexed or Non-Multiplexed
sors at Maximum Clock Frequency
and Function Capability)
Burn-In
CDP1881CE
CDP1882CE
CDP1882CEX
CLOCK
MWR
MRD
MA5
MA4
MA3
MA2
MA1
MA0
V
5V
SS
-
10
1
2
3
4
5
6
7
8
9
CDP1881C
TOP VIEW
CDP1882D
(PDIP)
|
Copyright
10V
-
-
-
18
17
16
15
14
13
12
©
20
19
11
-40 to +85
-40 to +85
-40 to +85
-40 to +85
Intersil Corporation 1999
RANGE
TEMP.
V
A8
A9
A10
A11
CS0
CS1
CS2
CS3
CE
(
o
DD
C)
CDP1882, CDP1882C
E20.3
E18.3
E18.3
D18.3
PKG.
NO.
4-1
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit
memory latch and decoder circuits intended for use in
CDP1800 series microprocessor systems. They can inter-
face directly with the multiplexed address bus of this system
at maximum clock frequency, and up to four 4K x 8-bit mem-
ories to provide a 16K byte memory system. With four 2K x
8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock input
to V
decoded outputs can be used in general purpose memory-
system applications.
The CDP1881C, CDP1882 and CDP1882C are intended for
use with 2K or 4K byte RAMs and are identical except that in
the CDP1882 MWR and MRD are excluded.
The CDP1882 is functionally identical to the CDP1882C. It
differs in that the CDP1882 has recommended operating
voltage range of 4V to 10.5V and the C version has a recom-
mended operating voltage range of 4V to 6.5V.
The CDP1881C, CDP1882 and CDP1882C are supplied in
20 lead and 18 lead packages, respectively. The
CDP1881C is supplied only in a dual-in-line plastic pack-
age (E suffix). The CDP1882 is supplied in dual-in-line,
hermetic side-brazed ceramic (D suffix) and in plastic (E
suffix) packages.
DD
, the latches are in the data-following mode and the
and Decoder Memory Interfaces
CLOCK
MA5
MA4
MA3
MA2
MA1
MA0
V
CE
SS
CDP1882, CDP1882C
(PDIP, CERDIP)
1
2
3
4
5
6
7
8
9
CDP1881C,
TOP VIEW
CMOS 6-Bit Latch
18
17
16
15
14
13
12
11
10
File Number
V
A8
A9
A10
A11
CS0
CS1
CS2
CS3
DD
1367.2

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CDP1881C Summary of contents

Page 1

... D18.3 The CDP1881C, CDP1882 and CDP1882C are supplied in 20 lead and 18 lead packages, respectively. The CDP1881C is supplied only in a dual-in-line plastic pack- age (E suffix). The CDP1882 is supplied in dual-in-line, hermetic side-brazed ceramic (D suffix) and in plastic (E suffix) packages. ...

Page 2

... Terminal) SS CDP1882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1881C and CDP1882C -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0. Input Current, Any One Input CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifi ...

Page 3

... MA3 MA4 MA5 CLOCK 1 MRD 8 MWR FIGURE 1. FUNCTIONAL DIAGRAM FOR THE CDP1881C CDP1881C, CDP1882, CDP1882C - + 5%, Except as Noted: (Continued CONDITIONS CDP1882 V V (NOTE (V) (V) MIN TYP ...

Page 4

... NOTE: 1. CDP1881C Only Logic 1 = High, Logic 0 = Low Don’t Care Dynamic Electrical Specifications PARAMETER Minimum Setup Time Memory Address to CLOCK Minimum Hold Time Memory Address After CLOCK Minimum CLOCK Pulse Width CDP1881C, CDP1882, CDP1882C ...

Page 5

... For CDP1881C type only. CE CS0, CS1, CS2, CS3 (A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY MRD OR MWR CS0, CS1, CS2, CS3 (B) MRD OR MWR TO CHIP SELECT PROPAGATION DELAY (CDP1881C ONLY) MA0 - MA5 CLOCK t CS0, CS1, CS2, CS3 A8 - A11 (C) MEMORY ADDRESS SETUP AND HOLD TIME ...

Page 6

... CE: CHIP ENABLE input - a low at the CE input of CDP1882, CDP1882C will enable the chip select decoder. A low at the CE input of CDP1881C, coincident with a low at either MRD or MRW pin, will enable the chip select decoder. A high on this pin forces CS0, CS1, CS2, and CS3 to a high (false) state ...

Page 7

... CDP1881C, CDP1882, CDP1882C WAIT CLR TPA CDP1800 ADDRESS BUS SERIES CPU MRD MWR FIGURE 5. CDP1800-SERIES SYSTEM USING THE CDP1882 CDP1882 LATCH/ DECODER CS3 CLK CS2 CS1 CE CS0 MA0 - MA5 A8 - A11 WAIT CLR A8 - A11 TPA CS2 ADDRESS BUS CDP1800 CDM5332 SERIES ...

Page 8

... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 CDP1881C, CDP1882, CDP1882C EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...

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